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Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructio

From: LIU Zhiwei
Subject: Re: [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions
Date: Thu, 18 Feb 2021 16:39:16 +0800
User-agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0

On 2021/2/13 2:03, Richard Henderson wrote:
On 2/12/21 7:02 AM, LIU Zhiwei wrote:
+    if (a->rd && a->rs1 && a->rs2) {
+#ifdef TARGET_RISCV64
+        f64(vece, offsetof(CPURISCVState, gpr[a->rd]),
+            offsetof(CPURISCVState, gpr[a->rs1]),
+            offsetof(CPURISCVState, gpr[a->rs2]),
+            8, 8);
This is not legal tcg.

You cannot reference as memory anything which has an associated tcg_global_mem.

Do you mean referringĀ  a global TCGTemp as memory will cause not consistent between TCGContext::temps and
CPUArchState field?

  Which is true for all of the gprs -- see riscv_translate_init.


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