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Re: [PATCH 1/3] Andes RISC-V PLIC
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From: |
Bin Meng |
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Subject: |
Re: [PATCH 1/3] Andes RISC-V PLIC |
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Date: |
Wed, 10 Mar 2021 14:05:51 +0800 |
On Wed, Mar 10, 2021 at 11:34 AM Dylan Jhong <dylan@andestech.com> wrote:
>
> Andes PLIC (Platform-Level Interrupt Controller) device provides an
> interrupt controller functionality based on Andes's PLIC specification.
>
> The Andes PLIC can handle either external interrupts (PLIC)
> or interprocessor interrupts (PLICSW).
>
> While Andes PLIC spec includes vector interrupt and interrupt preemption,
> we leave them as future items for now.
>
> Signed-off-by: Dylan Jhong <dylan@andestech.com>
> Signed-off-by: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
> ---
> hw/intc/Kconfig | 3 +
> hw/intc/andes_plic.c | 505 +++++++++++++++++++++++++++++++++++
> hw/intc/meson.build | 1 +
> include/hw/intc/andes_plic.h | 130 +++++++++
> 4 files changed, 639 insertions(+)
> create mode 100644 hw/intc/andes_plic.c
> create mode 100644 include/hw/intc/andes_plic.h
Is the Andes PLIC spec public available?
What's the difference between Andres's implementation and the SiFive's?
Regards,
Bin