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Re: [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions

From: Richard Henderson
Subject: Re: [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions
Date: Tue, 13 Apr 2021 20:42:51 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1

On 4/13/21 4:34 PM, Alistair Francis wrote:
-# ifdef TARGET_RISCV32
-#  define is_32bit(ctx)  true
-# else
+#ifdef TARGET_RISCV32
+# define is_32bit(ctx)  true
  static inline bool is_32bit(DisasContext *ctx)
-    return !(ctx->misa & RV64);
+    return (ctx->misa & RV32) == RV32;

Why the change here? Also note the previous comment about fixing this to false for TARGET_RISCV64 && CONFIG_USER_ONLY.

  static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_l_d *a)
      REQUIRE_EXT(ctx, RVD);
+    REQUIRE_64BIT(ctx);

I think you should always put the 64-bit check first.
That way, on TARGET_RISCV32, the entire function folds away.

- TCGv t0 = tcg_temp_new();
+    TCGv_i64 t0 = tcg_temp_new_i64();
      gen_set_rm(ctx, a->rm);
      gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
-    gen_set_gpr(a->rd, t0);
-    tcg_temp_free(t0);
+    gen_set_gpr(a->rd, (TCGv) t0);

So... I really don't like the cast.

This is fixable one of two ways.
(1) Change the real helper to use target_ulong.
(2) Use the gen_helper_* stubs that I talked about in reply to v1.

@@ -390,8 +390,9 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
      REQUIRE_EXT(ctx, RVD);
+    REQUIRE_64BIT(ctx);
- gen_set_gpr(a->rd, cpu_fpr[a->rs1]);
+    gen_set_gpr(a->rd, (TCGv) cpu_fpr[a->rs1]);

This one's different, and might be worth


+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -303,11 +303,11 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w 
TCGv t0 = tcg_temp_new(); -#if defined(TARGET_RISCV64)
-    tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
-    tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
+    if (!is_32bit(ctx)) {
+        tcg_gen_ext32s_tl((TCGv) t0, (TCGv) cpu_fpr[a->rs1]);
+    } else {
+        tcg_gen_extrl_i64_i32((TCGv_i32) t0, cpu_fpr[a->rs1]);
+    }

I think you should leave this ifdef alone. The ifdef has determined the size of target_ulong and thus the size of TCGv, and thus the correct move to use.

If TARGET_RISCV64 and is_32bit, the high bits are ignored; the fact that they happen to be copies of the sign bit is irrelevant.


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