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Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS

From: Jose Martins
Subject: Re: [PATCH v3] target/riscv: fix VS interrupts forwarding to HS
Date: Wed, 26 May 2021 12:50:32 +0100

Hello Zhiwei, thank you for reviewing the patch.

I'll split the patch in a series as you suggest. But first can you
help me understand what the problems are with

> I think there are two errors in riscv_cpu_local_irq_pending.
> 1) VS interrupts can't be forwarded to hs-mode rightly . It has
> nothing to do with delegate or not in hideleg. The reason is that
> VS interrupts are always discarded when V=0 in
> riscv_cpu_local_irq_pending.

I don't see why this is the case. The way I see it, VS interrupts are
only discarded for V=0 *iff* they are delegated in mideleg/hideleg.  I
actually tested it and I see the correct forwarding of vs-mode
interrupts to hs-mode. I tested it by running in hs-mode with all the
needed interrupt enables set, the interrupts not delegated in hideleg,
and forcing the trigger of the interrupt by writing hvip. But maybe
there are some corner cases I'm not taking into account. Can you
explain this further? Maybe walk me through an example of when this
issue might occur.

> 2) Use MSTATUS_SIE in mstatus_hs to select pending_hs_irqs.

I don't think you need to go through mstatus_hs to get the correct sie
state. My logic behind this is: env->mstatus will have the vs-level
sie if V=1 and hs-level sie if V=0. Due to the short-circuiting
property of the logic operators the sie variable will only have an
effect on hsie if V=0 and on vsie if V=1. So the value of sie is only
used in the correct context.

Again, please correct me if I'm wrong. I might be missing something.


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