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Re: TCG op for 32 bit only cpu on qemu-riscv64

From: LIU Zhiwei
Subject: Re: TCG op for 32 bit only cpu on qemu-riscv64
Date: Mon, 7 Jun 2021 17:22:44 +0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1

On 6/7/21 2:22 PM, Alistair Francis wrote:
On Mon, Jun 7, 2021 at 1:09 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
Hi Alistair,

As I see,  we are moving  on to remove TARGET_RISCV64 macro.

I have some questions:

1) Which tcg op should use when translate an instruction for 32bit cpu.
The tcg_*_i64, tcg_*_i32 or tcg_*_tl?
I see some API such as gen_get_gpr that are using the tcg_*_tl. But I am
not sure if it is
right for 32bit cpu.
Do you mean for an instruction that only runs on a 32-bit CPU (and not RV64)?

If the instruction only supports a 32-bit value then tcg_*_i32
otherwise tcg_*_tl is probably the best bet.

Thanks. I think you are right.

2) Do we should have a sign-extend 64 bit register(bit 31 as the sign
bit)  for 32 bit cpu?
I'm not clear what you mean. Can you point to a spec that you are
trying to implement?

I am implementing RVP to get rid of TARGET_RISCV64. After we have recognized an instruction only used by a 32-bit CPU,

1) Should we only use the lowest 32bits of the 64bits register in RV64?

TCGv s;
TCGv_i32 s32;
s = tcg_new_temp();
s32 = tcg_new_temp_i32();
gen_get_gpr(src1, a->rs1);
tcg_gen_trunc_tl_i32(s32, s);

Then we can use TCGv_i32 s32  to stand for rs1 register.

2) After some tcg ops(tcg_*_i32), when we write back to destination register, should we sign-extend
the 32 bit register before call get_set_gpr()?

Best Regards,


Best Regards,

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