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[PATCH v2 08/37] target/riscv: SIMD 8-bit Compare Instructions
From: |
LIU Zhiwei |
Subject: |
[PATCH v2 08/37] target/riscv: SIMD 8-bit Compare Instructions |
Date: |
Thu, 10 Jun 2021 15:58:39 +0800 |
There are 5 instructions here, including 8-bit compare
equal, signed less than, signed less than & equal,
unsigned less than, unsigned less than & equal.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 6 ++++
target/riscv/insn32.decode | 6 ++++
target/riscv/insn_trans/trans_rvp.c.inc | 7 ++++
target/riscv/packed_helper.c | 46 +++++++++++++++++++++++++
4 files changed, 65 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 830845761b..c424e45fe5 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1212,3 +1212,9 @@ DEF_HELPER_3(scmplt16, tl, env, tl, tl)
DEF_HELPER_3(scmple16, tl, env, tl, tl)
DEF_HELPER_3(ucmplt16, tl, env, tl, tl)
DEF_HELPER_3(ucmple16, tl, env, tl, tl)
+
+DEF_HELPER_3(cmpeq8, tl, env, tl, tl)
+DEF_HELPER_3(scmplt8, tl, env, tl, tl)
+DEF_HELPER_3(scmple8, tl, env, tl, tl)
+DEF_HELPER_3(ucmplt8, tl, env, tl, tl)
+DEF_HELPER_3(ucmple8, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5031cebf1f..fdbf3798c7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -815,3 +815,9 @@ scmplt16 0000110 ..... ..... 000 ..... 1110111 @r
scmple16 0001110 ..... ..... 000 ..... 1110111 @r
ucmplt16 0010110 ..... ..... 000 ..... 1110111 @r
ucmple16 0011110 ..... ..... 000 ..... 1110111 @r
+
+cmpeq8 0100111 ..... ..... 000 ..... 1110111 @r
+scmplt8 0000111 ..... ..... 000 ..... 1110111 @r
+scmple8 0001111 ..... ..... 000 ..... 1110111 @r
+ucmplt8 0010111 ..... ..... 000 ..... 1110111 @r
+ucmple8 0011111 ..... ..... 000 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 65199ffb5a..aa432701c8 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -210,3 +210,10 @@ GEN_RVP_R_OOL(scmplt16);
GEN_RVP_R_OOL(scmple16);
GEN_RVP_R_OOL(ucmplt16);
GEN_RVP_R_OOL(ucmple16);
+
+/* SIMD 8-bit Compare Instructions */
+GEN_RVP_R_OOL(cmpeq8);
+GEN_RVP_R_OOL(scmplt8);
+GEN_RVP_R_OOL(scmple8);
+GEN_RVP_R_OOL(ucmplt8);
+GEN_RVP_R_OOL(ucmple8);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 30b916b5ad..ff86e015e4 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -677,3 +677,49 @@ static inline void do_ucmple16(CPURISCVState *env, void
*vd, void *va,
}
RVPR(ucmple16, 1, 2);
+
+/* SIMD 8-bit Compare Instructions */
+static inline void do_cmpeq8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint8_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] == b[i]) ? 0xff : 0x0;
+}
+
+RVPR(cmpeq8, 1, 1);
+
+static inline void do_scmplt8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int8_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] < b[i]) ? 0xff : 0x0;
+}
+
+RVPR(scmplt8, 1, 1);
+
+static inline void do_scmple8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int8_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] <= b[i]) ? 0xff : 0x0;
+}
+
+RVPR(scmple8, 1, 1);
+
+static inline void do_ucmplt8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint8_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] < b[i]) ? 0xff : 0x0;
+}
+
+RVPR(ucmplt8, 1, 1);
+
+static inline void do_ucmple8(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint8_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] <= b[i]) ? 0xff : 0x0;
+}
+
+RVPR(ucmple8, 1, 1);
--
2.25.1
- [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions, (continued)
- [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 04/37] target/riscv: 8-bit Addition & Subtraction Instruction, LIU Zhiwei, 2021/06/10
- [PATCH v2 05/37] target/riscv: SIMD 16-bit Shift Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 06/37] target/riscv: SIMD 8-bit Shift Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 07/37] target/riscv: SIMD 16-bit Compare Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 08/37] target/riscv: SIMD 8-bit Compare Instructions,
LIU Zhiwei <=
- [PATCH v2 09/37] target/riscv: SIMD 16-bit Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 10/37] target/riscv: SIMD 8-bit Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/10