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[PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructi
From: |
LIU Zhiwei |
Subject: |
[PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions |
Date: |
Thu, 10 Jun 2021 15:59:06 +0800 |
32-bit rounding arithmetic shift right immediate.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvp.c.inc | 3 +++
target/riscv/packed_helper.c | 13 +++++++++++++
4 files changed, 20 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index aa80095e1d..b998c86abf 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1472,3 +1472,5 @@ DEF_HELPER_4(kmsxda32, tl, env, tl, tl, tl)
DEF_HELPER_3(smds32, i64, env, i64, i64)
DEF_HELPER_3(smdrs32, i64, env, i64, i64)
DEF_HELPER_3(smxds32, i64, env, i64, i64)
+
+DEF_HELPER_3(sraiw_u, i64, env, i64, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b9eeb57ca7..8e8aca4ea1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -1095,3 +1095,5 @@ kmsxda32 0100111 ..... ..... 010 ..... 1110111 @r
smds32 0101100 ..... ..... 010 ..... 1110111 @r
smdrs32 0110100 ..... ..... 010 ..... 1110111 @r
smxds32 0111100 ..... ..... 010 ..... 1110111 @r
+
+sraiw_u 0011010 ..... ..... 001 ..... 1110111 @sh5
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 48bcf37e36..68c1ef9f48 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1144,3 +1144,6 @@ GEN_RVP64_R_ACC_OOL(kmsxda32);
GEN_RVP64_R_OOL(smds32);
GEN_RVP64_R_OOL(smdrs32);
GEN_RVP64_R_OOL(smxds32);
+
+/* (RV64 Only) Non-SIMD 32-bit Shift Instructions */
+GEN_RVP64_SHIFTI(sraiw_u, gen_helper_sraiw_u);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 834e7dbebb..42f1d96fa5 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3795,3 +3795,16 @@ static inline void do_smxds32(CPURISCVState *env, void
*vd, void *va,
}
RVPR64_64_64(smxds32, 1, 8);
+
+/* (RV64 Only) Non-SIMD 32-bit Shift Instructions */
+static inline void do_sraiw_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va;
+ uint8_t shift = *(uint8_t *)vb;
+
+ *d = vssra32(env, 0, a[H4(i)], shift);
+}
+
+RVPR64_64_64(sraiw_u, 1, 8);
--
2.25.1
- [PATCH v2 25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions, (continued)
- [PATCH v2 25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions,
LIU Zhiwei <=
- [PATCH v2 36/37] target/riscv: RV64 Only 32-bit Packing Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 37/37] target/riscv: configure and turn on packed extension from command line, LIU Zhiwei, 2021/06/10
- Re: [PATCH v2 00/37] target/riscv: support packed extension v0.9.4, no-reply, 2021/06/14