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Re: [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs
From: |
Alistair Francis |
Subject: |
Re: [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs |
Date: |
Fri, 11 Jun 2021 09:15:38 +1000 |
On Sat, May 15, 2021 at 12:35 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> We add experimental CPU feature to enable AIA CSRs. This experimental
> feature can be enabled by setting "x-aia=true" for CPU in the QEMU
> command-line parameters.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> target/riscv/cpu.c | 5 +++++
> target/riscv/cpu.h | 4 +++-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7d6ed80f6b..f3702111ae 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -414,6 +414,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> set_feature(env, RISCV_FEATURE_PMP);
> }
>
> + if (cpu->cfg.aia) {
> + set_feature(env, RISCV_FEATURE_AIA);
> + }
> +
> set_resetvec(env, cpu->cfg.resetvec);
>
> /* If only XLEN is set for misa, then set misa from properties */
> @@ -554,6 +558,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> + DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
This line should be a seperate patch at the end of the series.
The idea is that we don't allow users to enable the feature until it
has been fully implemented.
Alistair
> DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
> DEFINE_PROP_END_OF_LIST(),
> };
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0a33d387ba..f00c60c840 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -80,7 +80,8 @@
> enum {
> RISCV_FEATURE_MMU,
> RISCV_FEATURE_PMP,
> - RISCV_FEATURE_MISA
> + RISCV_FEATURE_MISA,
> + RISCV_FEATURE_AIA
> };
>
> #define PRIV_VERSION_1_10_0 0x00011000
> @@ -303,6 +304,7 @@ struct RISCVCPU {
> uint16_t elen;
> bool mmu;
> bool pmp;
> + bool aia;
> uint64_t resetvec;
> } cfg;
> };
> --
> 2.25.1
>
>
- Re: [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs,
Alistair Francis <=