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[PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions
From: |
LIU Zhiwei |
Subject: |
[PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions |
Date: |
Thu, 24 Jun 2021 18:54:51 +0800 |
There are 5 instructions here, including 16-bit compare
equal, signed less than, signed less than & equal,
unsigned less than, unsigned less than & equal.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com
---
target/riscv/helper.h | 6 ++++
target/riscv/insn32.decode | 6 ++++
target/riscv/insn_trans/trans_rvp.c.inc | 7 ++++
target/riscv/packed_helper.c | 46 +++++++++++++++++++++++++
4 files changed, 65 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1b365135ff..830845761b 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1206,3 +1206,9 @@ DEF_HELPER_3(sll8, tl, env, tl, tl)
DEF_HELPER_3(ksll8, tl, env, tl, tl)
DEF_HELPER_3(kslra8, tl, env, tl, tl)
DEF_HELPER_3(kslra8_u, tl, env, tl, tl)
+
+DEF_HELPER_3(cmpeq16, tl, env, tl, tl)
+DEF_HELPER_3(scmplt16, tl, env, tl, tl)
+DEF_HELPER_3(scmple16, tl, env, tl, tl)
+DEF_HELPER_3(ucmplt16, tl, env, tl, tl)
+DEF_HELPER_3(ucmple16, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 8b78fb24bc..5031cebf1f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -809,3 +809,9 @@ ksll8 0110110 ..... ..... 000 ..... 1110111 @r
kslli8 0111110 01... ..... 000 ..... 1110111 @sh3
kslra8 0101111 ..... ..... 000 ..... 1110111 @r
kslra8_u 0110111 ..... ..... 000 ..... 1110111 @r
+
+cmpeq16 0100110 ..... ..... 000 ..... 1110111 @r
+scmplt16 0000110 ..... ..... 000 ..... 1110111 @r
+scmple16 0001110 ..... ..... 000 ..... 1110111 @r
+ucmplt16 0010110 ..... ..... 000 ..... 1110111 @r
+ucmple16 0011110 ..... ..... 000 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index e6c5f2ddf5..65199ffb5a 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -203,3 +203,10 @@ GEN_RVP_SHIFTI(slli8, tcg_gen_vec_shl8i_tl,
gen_helper_sll8);
GEN_RVP_SHIFTI(srai8_u, NULL, gen_helper_sra8_u);
GEN_RVP_SHIFTI(srli8_u, NULL, gen_helper_srl8_u);
GEN_RVP_SHIFTI(kslli8, NULL, gen_helper_ksll8);
+
+/* SIMD 16-bit Compare Instructions */
+GEN_RVP_R_OOL(cmpeq16);
+GEN_RVP_R_OOL(scmplt16);
+GEN_RVP_R_OOL(scmple16);
+GEN_RVP_R_OOL(ucmplt16);
+GEN_RVP_R_OOL(ucmple16);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index ab9ebc472b..30b916b5ad 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -631,3 +631,49 @@ static inline void do_kslra8_u(CPURISCVState *env, void
*vd, void *va,
}
RVPR(kslra8_u, 1, 1);
+
+/* SIMD 16-bit Compare Instructions */
+static inline void do_cmpeq16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint16_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] == b[i]) ? 0xffff : 0x0;
+}
+
+RVPR(cmpeq16, 1, 2);
+
+static inline void do_scmplt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int16_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] < b[i]) ? 0xffff : 0x0;
+}
+
+RVPR(scmplt16, 1, 2);
+
+static inline void do_scmple16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int16_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] <= b[i]) ? 0xffff : 0x0;
+}
+
+RVPR(scmple16, 1, 2);
+
+static inline void do_ucmplt16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint16_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] < b[i]) ? 0xffff : 0x0;
+}
+
+RVPR(ucmplt16, 1, 2);
+
+static inline void do_ucmple16(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ uint16_t *d = vd, *a = va, *b = vb;
+ d[i] = (a[i] <= b[i]) ? 0xffff : 0x0;
+}
+
+RVPR(ucmple16, 1, 2);
--
2.17.1
- [PATCH v3 00/37] target/riscv: support packed extension v0.9.4, LIU Zhiwei, 2021/06/24
- [PATCH v3 01/37] target/riscv: implementation-defined constant parameters, LIU Zhiwei, 2021/06/24
- [PATCH v3 02/37] target/riscv: Make the vector helper functions public, LIU Zhiwei, 2021/06/24
- [PATCH v3 03/37] target/riscv: 16-bit Addition & Subtraction Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 04/37] target/riscv: 8-bit Addition & Subtraction Instruction, LIU Zhiwei, 2021/06/24
- [PATCH v3 05/37] target/riscv: SIMD 16-bit Shift Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 06/37] target/riscv: SIMD 8-bit Shift Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 07/37] target/riscv: SIMD 16-bit Compare Instructions,
LIU Zhiwei <=
- [PATCH v3 08/37] target/riscv: SIMD 8-bit Compare Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 09/37] target/riscv: SIMD 16-bit Multiply Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 10/37] target/riscv: SIMD 8-bit Multiply Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 13/37] target/riscv: 8-bit Unpacking Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 14/37] target/riscv: 16-bit Packing Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions, LIU Zhiwei, 2021/06/24
- [PATCH v3 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/24