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Re: [PATCH 00/17] target/riscv: Use tcg_constant_*

From: Richard Henderson
Subject: Re: [PATCH 00/17] target/riscv: Use tcg_constant_*
Date: Thu, 15 Jul 2021 09:15:10 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 7/15/21 4:21 AM, LIU Zhiwei wrote:
Also on a side note, could you give me some advice for the following question?

I have been supporting  running 32bit application on qemu-riscv64. After this 
patch set,
it is hard to define a  method,  such as gpr_dst_s or gpr_dst_u, to extend the 
register. I can only extend the destination register(ext32s or ext32u) in each 
with scattered code.

Can we just omit the extension of the destination register?

It's hard to give advice on code that I haven't seen.

In general I would think that the destination register need not be extended for 32-bit mode, unless the architecture says otherwise. (What does the architecture say about the contents of the registers when transitioning from a 32-bit mode user program to a 64-bit mode kernel?)


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