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Re: [RFC PATCH 00/13] Support UXL field in mstatus
From: |
Bin Meng |
Subject: |
Re: [RFC PATCH 00/13] Support UXL field in mstatus |
Date: |
Thu, 5 Aug 2021 15:20:50 +0800 |
On Thu, Aug 5, 2021 at 3:16 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
> On 2021/8/5 下午2:01, Alistair Francis wrote:
> > On Thu, Aug 5, 2021 at 12:55 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> >> This patch set implements UXL field in mstatus register. Programmer can
> >> change
> >> UXLEN by writting to this field. So that you can run a 32 bit program
> >> on a 64 bit CPU.
> > Awesome! Do you have any steps for building a rootFS to test this?
>
> Not yet. It depends on Linux support which will not start until
> October. Maybe as a rough test,
> we can run the 32 glibc test cases on qemu-riscv64 with an option
> uxl32=true(not implement yet).
That's my understanding as well. Currently there is no software stack
that supports mode switch, e.g.: OpenSBI boots in 64-bit but loading a
32-bit payload to execute.
Do you plan to support SXL as well?
Regards,
Bin
- Re: [RFC PATCH 06/13] target/riscv: Fix div instructions, (continued)
- [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM, LIU Zhiwei, 2021/08/04
- [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions, LIU Zhiwei, 2021/08/04
- [RFC PATCH 11/13] target/riscv: Fix srow, LIU Zhiwei, 2021/08/04
- [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB, LIU Zhiwei, 2021/08/04
- [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR, LIU Zhiwei, 2021/08/04
- Re: [RFC PATCH 00/13] Support UXL field in mstatus, Alistair Francis, 2021/08/05