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Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instruction

From: LIU Zhiwei
Subject: Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions
Date: Thu, 12 Aug 2021 15:20:26 +0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 2021/8/12 下午2:12, Richard Henderson wrote:
On 8/11/21 7:03 PM, LIU Zhiwei wrote:

On 2021/8/12 下午12:42, Richard Henderson wrote:
On 8/11/21 12:40 PM, LIU Zhiwei wrote:
If the software doesn't use the high part, who cares the really value in high part? Do you know the benefit?  Thanks again.

I do not.

I simply presume that they already have the hardware, in the form of the addw instruction, etc.

The mistake, I think, was changing the definition of "add" in the first place, which required the addition of a different opcode "addw", which is then undefined for RV32.

Sorry, I don't get "the mistake" here. Do you think the specification is not right.

I was critiquing the development of the risc-v specification, in that there are complications in the current specification that could have been foreseen and avoided with different choices years ago.

They should simply have had "addw" and "addq" as different opcodes that didn't change behaviour. Etc.

I don't get  this statement. Is it related to UXL32?

No.  I was just musing.  It's not important.

Although I don't know what really you mean, I think "addw" and "addq" will be better than current "addw" and "add".
At least we can avoid adjust almost every instruction like "add" for UXL32.

Best Regards,


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