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Re: [PATCH v5 13/24] target/riscv: Use extracts for sraiw and srliw
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v5 13/24] target/riscv: Use extracts for sraiw and srliw |
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Date: |
Wed, 25 Aug 2021 16:07:59 +1000 |
On Tue, Aug 24, 2021 at 6:05 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> These operations can be done in one instruction on some hosts.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index e4726e618c..9e8d99be51 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -347,18 +347,28 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
> return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
> }
>
> +static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
> +{
> + tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
> +}
> +
> static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
> {
> REQUIRE_64BIT(ctx);
> ctx->w = true;
> - return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
> + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
> +}
> +
> +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
> +{
> + tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
> }
>
> static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
> {
> REQUIRE_64BIT(ctx);
> ctx->w = true;
> - return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
> + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
> }
>
> static bool trans_addw(DisasContext *ctx, arg_addw *a)
> --
> 2.25.1
>
>
- [PATCH v5 09/24] target/riscv: Move gen_* helpers for RVM, (continued)
- [PATCH v5 09/24] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/23
- [PATCH v5 11/24] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/23
- [PATCH v5 10/24] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/23
- [PATCH v5 14/24] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/23
- [PATCH v5 12/24] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/23
- [PATCH v5 16/24] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation, Richard Henderson, 2021/08/23
- [PATCH v5 13/24] target/riscv: Use extracts for sraiw and srliw, Richard Henderson, 2021/08/23
- [PATCH v5 15/24] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/23
- [PATCH v5 17/24] target/riscv: Fix hgeie, hgeip, Richard Henderson, 2021/08/23
- [PATCH v5 18/24] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/23
- [PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/23
- [PATCH v5 19/24] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/23