Re: [PATCH v5 21/24] target/riscv: Use {get,dest}

qemu-riscv

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Re: [PATCH v5 21/24] target/riscv: Use {get,dest}_gpr for RVF

From:	Alistair Francis
Subject:	Re: [PATCH v5 21/24] target/riscv: Use {get,dest}_gpr for RVF
Date:	Wed, 25 Aug 2021 16:17:33 +1000

On Tue, Aug 24, 2021 at 6:04 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvf.c.inc | 146 ++++++++++++------------
>  1 file changed, 70 insertions(+), 76 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvf.c.inc 
> b/target/riscv/insn_trans/trans_rvf.c.inc
> index fb9f7f9c00..bddbd418d9 100644
> --- a/target/riscv/insn_trans/trans_rvf.c.inc
> +++ b/target/riscv/insn_trans/trans_rvf.c.inc
> @@ -25,32 +25,43 @@
>
>  static bool trans_flw(DisasContext *ctx, arg_flw *a)
>  {
> +    TCGv_i64 dest;
> +    TCGv addr;
> +
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> -    tcg_gen_addi_tl(t0, t0, a->imm);
>
> -    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
> -    gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
> +    addr = get_gpr(ctx, a->rs1, EXT_NONE);
> +    if (a->imm) {
> +        TCGv temp = temp_new(ctx);
> +        tcg_gen_addi_tl(temp, addr, a->imm);
> +        addr = temp;
> +    }
> +
> +    dest = cpu_fpr[a->rd];
> +    tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
> +    gen_nanbox_s(dest, dest);
>
> -    tcg_temp_free(t0);
>      mark_fs_dirty(ctx);
>      return true;
>  }
>
>  static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
>  {
> +    TCGv addr;
> +
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
>
> -    tcg_gen_addi_tl(t0, t0, a->imm);
> +    addr = get_gpr(ctx, a->rs1, EXT_NONE);
> +    if (a->imm) {
> +        TCGv temp = tcg_temp_new();
> +        tcg_gen_addi_tl(temp, addr, a->imm);
> +        addr = temp;
> +    }
>
> -    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
> +    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
>
> -    tcg_temp_free(t0);
>      return true;
>  }
>
> @@ -271,12 +282,11 @@ static bool trans_fcvt_w_s(DisasContext *ctx, 
> arg_fcvt_w_s *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    TCGv dest = dest_gpr(ctx, a->rd);
>
> +    gen_set_rm(ctx, a->rm);
> +    gen_helper_fcvt_w_s(dest, cpu_env, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -285,12 +295,11 @@ static bool trans_fcvt_wu_s(DisasContext *ctx, 
> arg_fcvt_wu_s *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    TCGv dest = dest_gpr(ctx, a->rd);
>
> +    gen_set_rm(ctx, a->rm);
> +    gen_helper_fcvt_wu_s(dest, cpu_env, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -300,17 +309,15 @@ static bool trans_fmv_x_w(DisasContext *ctx, 
> arg_fmv_x_w *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> +    TCGv dest = dest_gpr(ctx, a->rd);
>
>  #if defined(TARGET_RISCV64)
> -    tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]);
> +    tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]);
>  #else
> -    tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]);
> +    tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
>  #endif
>
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> -
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -318,10 +325,11 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a)
>  {
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
> -    TCGv t0 = tcg_temp_new();
> -    gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +
> +    gen_helper_feq_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -329,10 +337,11 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a)
>  {
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
> -    TCGv t0 = tcg_temp_new();
> -    gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +
> +    gen_helper_flt_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -340,10 +349,11 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a)
>  {
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
> -    TCGv t0 = tcg_temp_new();
> -    gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +
> +    gen_helper_fle_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -352,13 +362,10 @@ static bool trans_fclass_s(DisasContext *ctx, 
> arg_fclass_s *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> -
> -    gen_helper_fclass_s(t0, cpu_fpr[a->rs1]);
> -
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    TCGv dest = dest_gpr(ctx, a->rd);
>
> +    gen_helper_fclass_s(dest, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -367,15 +374,12 @@ static bool trans_fcvt_s_w(DisasContext *ctx, 
> arg_fcvt_s_w *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
>
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0);
> +    gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, src);
>
>      mark_fs_dirty(ctx);
> -    tcg_temp_free(t0);
> -
>      return true;
>  }
>
> @@ -384,15 +388,12 @@ static bool trans_fcvt_s_wu(DisasContext *ctx, 
> arg_fcvt_s_wu *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
>
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0);
> +    gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, src);
>
>      mark_fs_dirty(ctx);
> -    tcg_temp_free(t0);
> -
>      return true;
>  }
>
> @@ -402,15 +403,12 @@ static bool trans_fmv_w_x(DisasContext *ctx, 
> arg_fmv_w_x *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
>
> -    tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0);
> +    tcg_gen_extu_tl_i64(cpu_fpr[a->rd], src);
>      gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]);
>
>      mark_fs_dirty(ctx);
> -    tcg_temp_free(t0);
> -
>      return true;
>  }
>
> @@ -420,11 +418,11 @@ static bool trans_fcvt_l_s(DisasContext *ctx, 
> arg_fcvt_l_s *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    gen_helper_fcvt_l_s(dest, cpu_env, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -434,11 +432,11 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, 
> arg_fcvt_lu_s *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    gen_helper_fcvt_lu_s(dest, cpu_env, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -448,14 +446,12 @@ static bool trans_fcvt_s_l(DisasContext *ctx, 
> arg_fcvt_s_l *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
>
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0);
> +    gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, src);
>
>      mark_fs_dirty(ctx);
> -    tcg_temp_free(t0);
>      return true;
>  }
>
> @@ -465,13 +461,11 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, 
> arg_fcvt_s_lu *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVF);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
>
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0);
> +    gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, src);
>
>      mark_fs_dirty(ctx);
> -    tcg_temp_free(t0);
>      return true;
>  }
> --
> 2.25.1
>
>

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Re: [PATCH v5 18/24] target/riscv: Reorg csr instructions, (continued)
- [PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw, Alistair Francis, 2021/08/25
- [PATCH v5 19/24] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 19/24] target/riscv: Use {get,dest}_gpr for RVA, Alistair Francis, 2021/08/25
- [PATCH v5 23/24] target/riscv: Tidy trans_rvh.c.inc, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 23/24] target/riscv: Tidy trans_rvh.c.inc, Alistair Francis, 2021/08/30
- [PATCH v5 22/24] target/riscv: Use {get,dest}_gpr for RVD, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 22/24] target/riscv: Use {get,dest}_gpr for RVD, Alistair Francis, 2021/08/25
- [PATCH v5 21/24] target/riscv: Use {get,dest}_gpr for RVF, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 21/24] target/riscv: Use {get,dest}_gpr for RVF, Alistair Francis <=
- [PATCH v5 24/24] target/riscv: Use {get,dest}_gpr for RVV, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 24/24] target/riscv: Use {get,dest}_gpr for RVV, Alistair Francis, 2021/08/30

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