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Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instruc
Re: [PATCH 3/8] target/riscv: Addition of 128-bit ldu, lq and sq instructions
Mon, 30 Aug 2021 23:35:35 +0200
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On 8/30/21 7:16 PM, Frédéric Pétrot wrote:
> Addition of the load(s) and store instructions of the 128-bit extension.
> These instructions have addresses on 128-bit but explicitly assume that the
> upper 64-bit of the address registers is null, and therefore can use the
> existing address translation mechanism.
> 128-bit memory access identification and 64-bit signedness is handled a bit
> MemOp reserves 2 bits for size and a contiguous 3rd bit for the sign, so we
> cannot simply take value 4 to indicate a size of 16 bytes.
> Additionally, MO_TEQ | MO_SIGN seems to be a sentinel value, leading to a
> QEMU assertion violation.
> Modifying the existing state in QEMU has a great impact that we are not
> capable of fully evaluating, so we choose to pass this information into
> another parameter and let memop as it is for now.
> Signed-off-by: Frédéric Pétrot <email@example.com>
> Co-authored-by: Fabien Portas <firstname.lastname@example.org>
> include/tcg/tcg-op.h | 1 +
> tcg/tcg-op.c | 6 +
Please split in 2 patches, first TCG generic,
> target/riscv/insn16.decode | 33 ++++-
> target/riscv/insn32.decode | 5 +
> target/riscv/insn_trans/trans_rvi.c.inc | 188 +++++++++++++++++++++---
Second particular RISCV implementation.
> 5 files changed, 207 insertions(+), 26 deletions(-)