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Re: [PATCH 0/8] RISC V partial support for 128-bit architecture

From: Alistair Francis
Subject: Re: [PATCH 0/8] RISC V partial support for 128-bit architecture
Date: Tue, 31 Aug 2021 13:15:25 +1000

On Tue, Aug 31, 2021 at 5:29 AM Frédéric Pétrot
<frederic.petrot@univ-grenoble-alpes.fr> wrote:
> This series of patches aims at adding partial 128-bit support to the riscv
> target, following the (unratified) RV128I specification, Chapter 7 of
> riscv-spec document dated 20191214.
> It provides support for all user integer (I) instructions and for an M
> extension which follows the definition of the 32 and 64-bit specifications.
> We also included minimal support for 128-bit csrs.
> Among the csrs, we selected misa, to know the mxlen in which the processor
> is, mtvec, mepc, mscratch and mstatus for minimal kernel development, and
> satp to point to the page table.
> We fallback on the 64-bit csrs for the others.
> In the last patch, we propose a "natural" extension of the sv39 and sv48
> virtual address modes using 16KB pages, that we believe suitable for
> 128-bit CPU workloads.
> There are two strong assumptions in this implementation:
> - the 64 upper bits of the addresses are irrelevant, be they virtual or
>   physical, in order to use the existing address translation mechanism,
> - the mxlen field stays hardwired, so there is no dynamic change in
>   register size.
> As no toolchain exists yet for this target, we wrote all our tests in asm
> using macros expanding .insn directives.
> We unit tested the behavior of the instructions, and wrote some simple
> user level performance tests: on our examples the execution speed of the
> 128-bit version is between 1.2 to 5 time slower than its 32 and 64-bit
> counterparts.

Are you able to share these tests? I would like to add them to my
RISC-V tests so that I can catch any regressions


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