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[PATCH v1 2/2] target/riscv: Set mtval and stval support
From: |
Alistair Francis |
Subject: |
[PATCH v1 2/2] target/riscv: Set mtval and stval support |
Date: |
Fri, 3 Sep 2021 09:23:48 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 1 +
target/riscv/cpu.c | 6 +++++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6d41a16ae3..64ebb593fb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -309,6 +309,7 @@ struct RISCVCPU {
bool mmu;
bool pmp;
bool epmp;
+ bool mtval_inst;
uint64_t resetvec;
} cfg;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1a2b03d579..8b77526c79 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -437,6 +437,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
}
+ if (cpu->cfg.mtval_inst) {
+ set_feature(env, RISCV_FEATURE_MTVAL_INST);
+ }
+
set_resetvec(env, cpu->cfg.resetvec);
/* If only XLEN is set for misa, then set misa from properties */
@@ -600,7 +604,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
-
+ DEFINE_PROP_BOOL("mtval_inst", RISCVCPU, cfg.mtval_inst, true),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),
};
--
2.31.1