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Re: [ RFC v2 2/9] target/riscv: pmu: Rename the counters extension to pm
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From: |
Bin Meng |
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Subject: |
Re: [ RFC v2 2/9] target/riscv: pmu: Rename the counters extension to pmu |
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Date: |
Wed, 15 Sep 2021 22:49:52 +0800 |
On Fri, Sep 10, 2021 at 4:27 AM Atish Patra <atish.patra@wdc.com> wrote:
>
> The PMU counters are supported via cpu config "Counters" which doesn't
> indicate the correct purpose of those counters.
>
> Rename the config property to pmu to indicate that these counters
> are performance monitoring counters. This aligns with cpu options for
> ARM architecture as well.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 2 +-
> target/riscv/csr.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 991a6bb7604f..7a486450ebc6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -587,7 +587,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
> DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> + DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index bf1c899c00b8..5e67003e58a3 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -293,7 +293,7 @@ struct RISCVCPU {
> bool ext_u;
> bool ext_h;
> bool ext_v;
> - bool ext_counters;
> + bool ext_pmu;
> bool ext_ifencei;
> bool ext_icsr;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 0515d851b948..c3ce7d83a6b2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -64,7 +64,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> RISCVCPU *cpu = RISCV_CPU(cs);
> int ctr_index;
>
> - if (!cpu->cfg.ext_counters) {
> + if (!cpu->cfg.ext_pmu) {
> /* The Counters extensions is not enabled */
The PMU extension
> return RISCV_EXCP_ILLEGAL_INST;
> }
> --
Otherwise,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- [ RFC v2 0/9] Improve PMU support, Atish Patra, 2021/09/09
- [ RFC v2 1/9] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2021/09/09
- [ RFC v2 8/9] target/riscv: Add few cache related PMU events, Atish Patra, 2021/09/09
- [ RFC v2 2/9] target/riscv: pmu: Rename the counters extension to pmu, Atish Patra, 2021/09/09
- [ RFC v2 3/9] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2021/09/09
- [ RFC v2 7/9] target/riscv: Add sscofpmf extension support, Atish Patra, 2021/09/09
- [ RFC v2 6/9] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2021/09/09
- [ RFC v2 9/9] hw/riscv: virt: Add PMU DT node to the device tree, Atish Patra, 2021/09/09
- [ RFC v2 4/9] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2021/09/09