[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/f

From: Richard Henderson
Subject: Re: [PATCH v3 2/2] target/riscv: change the api for single/double fmin/fmax
Date: Fri, 15 Oct 2021 10:05:50 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/14/21 11:54 PM, frank.chang@sifive.com wrote:
From: Chih-Min Chao<chihmin.chao@sifive.com>

The sNaN propagation behavior has been changed since
cd20cee7 inhttps://github.com/riscv/riscv-isa-manual

Signed-off-by: Chih-Min Chao<chihmin.chao@sifive.com>
  target/riscv/fpu_helper.c | 8 ++++----
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 8700516a14c..1472ead2528 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -174,14 +174,14 @@ uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, 
uint64_t rs2)
      float32 frs1 = check_nanbox_s(rs1);
      float32 frs2 = check_nanbox_s(rs2);
-    return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status));
+    return nanbox_s(float32_minnum_noprop(frs1, frs2, &env->fp_status));

Don't you need to conditionalize behaviour on the isa revision?


reply via email to

[Prev in Thread] Current Thread [Next in Thread]