Re: [PATCH v3 13/14] target/riscv: Use gen_shift*_per

qemu-riscv

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Re: [PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI

From:	Alistair Francis
Subject:	Re: [PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI
Date:	Mon, 18 Oct 2021 14:43:10 +1000

On Sun, Oct 17, 2021 at 3:28 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Most shift instructions require a separate implementation
> for RV32 when TARGET_LONG_BITS == 64.
>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c                | 31 +++++++++
>  target/riscv/insn_trans/trans_rvb.c.inc | 92 ++++++++++++++-----------
>  target/riscv/insn_trans/trans_rvi.c.inc | 26 +++----
>  3 files changed, 97 insertions(+), 52 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 7286791c0f..0b3da060fd 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -463,6 +463,22 @@ static bool gen_shift_imm_fn(DisasContext *ctx, 
> arg_shift *a, DisasExtend ext,
>      return true;
>  }
>
> +static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
> +                                    DisasExtend ext,
> +                                    void (*f_tl)(TCGv, TCGv, target_long),
> +                                    void (*f_32)(TCGv, TCGv, target_long))
> +{
> +    int olen = get_olen(ctx);
> +    if (olen != TARGET_LONG_BITS) {
> +        if (olen == 32) {
> +            f_tl = f_32;
> +        } else {
> +            g_assert_not_reached();
> +        }
> +    }
> +    return gen_shift_imm_fn(ctx, a, ext, f_tl);
> +}
> +
>  static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend 
> ext,
>                               void (*func)(TCGv, TCGv, TCGv))
>  {
> @@ -499,6 +515,21 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, 
> DisasExtend ext,
>      return true;
>  }
>
> +static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
> +                             void (*f_tl)(TCGv, TCGv, TCGv),
> +                             void (*f_32)(TCGv, TCGv, TCGv))
> +{
> +    int olen = get_olen(ctx);
> +    if (olen != TARGET_LONG_BITS) {
> +        if (olen == 32) {
> +            f_tl = f_32;
> +        } else {
> +            g_assert_not_reached();
> +        }
> +    }
> +    return gen_shift(ctx, a, ext, f_tl);
> +}
> +
>  static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
>                        void (*func)(TCGv, TCGv))
>  {
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index 0c2120428d..cc39e6033b 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -227,22 +227,70 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
>      return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
>  }
>
> +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv_i32 t1 = tcg_temp_new_i32();
> +    TCGv_i32 t2 = tcg_temp_new_i32();
> +
> +    /* truncate to 32-bits */
> +    tcg_gen_trunc_tl_i32(t1, arg1);
> +    tcg_gen_trunc_tl_i32(t2, arg2);
> +
> +    tcg_gen_rotr_i32(t1, t1, t2);
> +
> +    /* sign-extend 64-bits */
> +    tcg_gen_ext_i32_tl(ret, t1);
> +
> +    tcg_temp_free_i32(t1);
> +    tcg_temp_free_i32(t2);
> +}
> +
>  static bool trans_ror(DisasContext *ctx, arg_ror *a)
>  {
>      REQUIRE_ZBB(ctx);
> -    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
> +    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw);
> +}
> +
> +static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
> +{
> +    TCGv_i32 t1 = tcg_temp_new_i32();
> +
> +    tcg_gen_trunc_tl_i32(t1, arg1);
> +    tcg_gen_rotri_i32(t1, t1, shamt);
> +    tcg_gen_ext_i32_tl(ret, t1);
> +
> +    tcg_temp_free_i32(t1);
>  }
>
>  static bool trans_rori(DisasContext *ctx, arg_rori *a)
>  {
>      REQUIRE_ZBB(ctx);
> -    return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
> +    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
> +                                   tcg_gen_rotri_tl, gen_roriw);
> +}
> +
> +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv_i32 t1 = tcg_temp_new_i32();
> +    TCGv_i32 t2 = tcg_temp_new_i32();
> +
> +    /* truncate to 32-bits */
> +    tcg_gen_trunc_tl_i32(t1, arg1);
> +    tcg_gen_trunc_tl_i32(t2, arg2);
> +
> +    tcg_gen_rotl_i32(t1, t1, t2);
> +
> +    /* sign-extend 64-bits */
> +    tcg_gen_ext_i32_tl(ret, t1);
> +
> +    tcg_temp_free_i32(t1);
> +    tcg_temp_free_i32(t2);
>  }
>
>  static bool trans_rol(DisasContext *ctx, arg_rol *a)
>  {
>      REQUIRE_ZBB(ctx);
> -    return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
> +    return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw);
>  }
>
>  static void gen_rev8_32(TCGv ret, TCGv src1)
> @@ -349,24 +397,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
>      return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
>  }
>
> -static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> -    TCGv_i32 t1 = tcg_temp_new_i32();
> -    TCGv_i32 t2 = tcg_temp_new_i32();
> -
> -    /* truncate to 32-bits */
> -    tcg_gen_trunc_tl_i32(t1, arg1);
> -    tcg_gen_trunc_tl_i32(t2, arg2);
> -
> -    tcg_gen_rotr_i32(t1, t1, t2);
> -
> -    /* sign-extend 64-bits */
> -    tcg_gen_ext_i32_tl(ret, t1);
> -
> -    tcg_temp_free_i32(t1);
> -    tcg_temp_free_i32(t2);
> -}
> -
>  static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
>  {
>      REQUIRE_64BIT(ctx);
> @@ -380,25 +410,7 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
>      REQUIRE_64BIT(ctx);
>      REQUIRE_ZBB(ctx);
>      ctx->ol = MXL_RV32;
> -    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_rorw);
> -}
> -
> -static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> -    TCGv_i32 t1 = tcg_temp_new_i32();
> -    TCGv_i32 t2 = tcg_temp_new_i32();
> -
> -    /* truncate to 32-bits */
> -    tcg_gen_trunc_tl_i32(t1, arg1);
> -    tcg_gen_trunc_tl_i32(t2, arg2);
> -
> -    tcg_gen_rotl_i32(t1, t1, t2);
> -
> -    /* sign-extend 64-bits */
> -    tcg_gen_ext_i32_tl(ret, t1);
> -
> -    tcg_temp_free_i32(t1);
> -    tcg_temp_free_i32(t2);
> +    return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw);
>  }
>
>  static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index c0a46d823f..b0fdec97de 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -270,14 +270,26 @@ static bool trans_slli(DisasContext *ctx, arg_slli *a)
>      return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
>  }
>
> +static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
> +{
> +    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
> +}
> +
>  static bool trans_srli(DisasContext *ctx, arg_srli *a)
>  {
> -    return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
> +    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
> +                                   tcg_gen_shri_tl, gen_srliw);
> +}
> +
> +static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
> +{
> +    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
>  }
>
>  static bool trans_srai(DisasContext *ctx, arg_srai *a)
>  {
> -    return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
> +    return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
> +                                   tcg_gen_sari_tl, gen_sraiw);
>  }
>
>  static bool trans_add(DisasContext *ctx, arg_add *a)
> @@ -344,11 +356,6 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
>      return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
>  }
>
> -static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
> -{
> -    tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
> -}
> -
>  static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
>  {
>      REQUIRE_64BIT(ctx);
> @@ -356,11 +363,6 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
>      return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
>  }
>
> -static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
> -{
> -    tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
> -}
> -
>  static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
>  {
>      REQUIRE_64BIT(ctx);
> --
> 2.25.1
>
>

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Re: [PATCH v3 12/14] target/riscv: Use gen_unary_per_ol for RVB, (continued)
- [PATCH v3 11/14] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/16
- [PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/16
  - Re: [PATCH v3 10/14] target/riscv: Use gen_arith_per_ol for RVM, Alistair Francis, 2021/10/18
- [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/16
  - Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand, Alistair Francis, 2021/10/18
    - Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/18
    - Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand, Alistair Francis, 2021/10/18
    - Re: [PATCH v3 14/14] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/18
- [PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/16
  - Re: [PATCH v3 13/14] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Alistair Francis <=

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