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Re: [PATCH v8 00/78] support vector extension v1.0

From: LIU Zhiwei
Subject: Re: [PATCH v8 00/78] support vector extension v1.0
Date: Mon, 18 Oct 2021 17:34:47 +0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

Hi Alistair,

Sorry for the  send error.  And I have a question about this patch set.

Firstly, I totally support the vector v1.0 upstream.

The concern is how to deal with the v0.7.1 code on QEMU. There are some products based on the vector v0.7.1, such as D1 SOC from Allwinner and  Xuantie CPU  from Alibaba. The Linux and GCC upstream for D1 is working in progress, and eventually these projects will support v0.7.1 in some way, probably as "x-thead-v" (the "thead" stands for Alibaba T-Head).

Maybe we can

1. Drop the v0.7.1 support permanently.

2. Drop the v0.7.1  temporarily and add  it  back later.

3. Do some compatible work for v0.7.1 in the v1.0 patch set.

Look forward to your idea. Thanks very much.

Best Regards,

On 2021/10/18 下午5:01, LIU Zhiwei wrote:
Hi Alistair,

There is some products based on the vector v0.7.1, such as D1 SOC from Allwinner and  Xuantie CPU  And we have spent a lot of work to support  vector  on QEMU.


On 2021/10/15 下午3:45, frank.chang@sifive.com wrote:
From: Frank Chang <frank.chang@sifive.com>

This patchset implements the vector extension v1.0 for RISC-V on QEMU.

RVV v1.0 spec is now fronzen for public review:

The port is available here:

RVV v1.0 can be enabled with -cpu option: v=true and specify vext_spec
option to v1.0 (i.e. vext_spec=v1.0)

Note: This patchset depends on other patchsets listed in Based-on
       section below so it is not able to be built unless those patchsets
       are applied.


   * Use {get,dest}_gpr APIs.
   * remove vector AMO instructions.
   * rename vpopc.m to vcpop.m.
   * rename vle1.v and vse1.v to vlm.v and vsm.v.
   * rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm.

   * remove hardcoded GDB vector registers list.
   * add vsetivli instruction.
   * add vle1.v and vse1.v instructions.

   * add vector floating-point reciprocal estimate instruction.
   * add vector floating-point reciprocal square-root estimate instruction.    * update check rules for segment register groups, each segment register
     group has to follow overlap rules.
   * update viota.m instruction check rules.

   * refactor RVV v1.0 check functions.
     (Thanks to Richard Henderson's bitwise tricks.)
   * relax RV_VLEN_MAX to 1024-bits.
   * implement vstart CSR's behaviors.
   * trigger illegal instruction exception if frm is not valid for
     vector floating-point instructions.
   * rebase on riscv-to-apply.next.

   * remove explicit float flmul variable in DisasContext.
   * replace floating-point calculations with shift operations to
     improve performance.
   * relax RV_VLEN_MAX to 512-bits.

   * apply nan-box helpers from Richard Henderson.
   * remove fp16 api changes as they are sent independently in another
     pathcset by Chih-Min Chao.
   * remove all tail elements clear functions as tail elements can
     retain unchanged for either VTA set to undisturbed or agnostic.
   * add fp16 nan-box check generator function.
   * add floating-point rounding mode enum.
   * replace flmul arithmetic with shifts to avoid floating-point
   * add Zvqmac extension.
   * replace gdbstub vector register xml files with dynamic generator.
   * bumped to RVV v1.0.
   * RVV v1.0 related changes:
     * add vl<nf>re<eew>.v and vs<nf>r.v vector whole register
       load/store instructions
     * add vrgatherei16 instruction.
     * rearranged bits in vtype to make vlmul bits into a contiguous

   * drop v0.7.1 support.
   * replace invisible return check macros with functions.
   * move mark_vs_dirty() to translators.
   * add SSTATUS_VS flag for s-mode.
   * nan-box scalar fp register for floating-point operations.
   * add gdbstub files for vector registers to allow system-mode
     debugging with GDB.

Based-on: <20211015065500.3850513-1-frank.chang@sifive.com>
Based-on: <20211015070307.3860984-1-frank.chang@sifive.com>

Frank Chang (73):
   target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
   target/riscv: drop vector 0.7.1 and add 1.0 support
   target/riscv: Use FIELD_EX32() to extract wd field
   target/riscv: rvv-1.0: introduce writable misa.v field
   target/riscv: rvv-1.0: add translation-time vector context status
   target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
   target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr
   target/riscv: rvv-1.0: remove MLEN calculations
   target/riscv: rvv-1.0: add fractional LMUL
   target/riscv: rvv-1.0: add VMA and VTA
   target/riscv: rvv-1.0: update check functions
   target/riscv: introduce more imm value modes in translator functions
   target/riscv: rvv:1.0: add translation-time nan-box helper function
   target/riscv: rvv-1.0: remove amo operations instructions
   target/riscv: rvv-1.0: configure instructions
   target/riscv: rvv-1.0: stride load and store instructions
   target/riscv: rvv-1.0: index load and store instructions
   target/riscv: rvv-1.0: fix address index overflow bug of indexed
     load/store insns
   target/riscv: rvv-1.0: fault-only-first unit stride load
   target/riscv: rvv-1.0: load/store whole register instructions
   target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
   target/riscv: rvv-1.0: take fractional LMUL into vector max elements
   target/riscv: rvv-1.0: floating-point square-root instruction
   target/riscv: rvv-1.0: floating-point classify instructions
   target/riscv: rvv-1.0: count population in mask instruction
   target/riscv: rvv-1.0: find-first-set mask bit instruction
   target/riscv: rvv-1.0: set-X-first mask bit instructions
   target/riscv: rvv-1.0: iota instruction
   target/riscv: rvv-1.0: element index instruction
   target/riscv: rvv-1.0: allow load element with sign-extended
   target/riscv: rvv-1.0: register gather instructions
   target/riscv: rvv-1.0: integer scalar move instructions
   target/riscv: rvv-1.0: floating-point move instruction
   target/riscv: rvv-1.0: floating-point scalar move instructions
   target/riscv: rvv-1.0: whole register move instructions
   target/riscv: rvv-1.0: integer extension instructions
   target/riscv: rvv-1.0: single-width averaging add and subtract
   target/riscv: rvv-1.0: single-width bit shift instructions
   target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
   target/riscv: rvv-1.0: narrowing integer right shift instructions
   target/riscv: rvv-1.0: widening integer multiply-add instructions
   target/riscv: rvv-1.0: single-width saturating add and subtract
   target/riscv: rvv-1.0: integer comparison instructions
   target/riscv: rvv-1.0: floating-point compare instructions
   target/riscv: rvv-1.0: mask-register logical instructions
   target/riscv: rvv-1.0: slide instructions
   target/riscv: rvv-1.0: floating-point slide instructions
   target/riscv: rvv-1.0: narrowing fixed-point clip instructions
   target/riscv: rvv-1.0: single-width floating-point reduction
   target/riscv: rvv-1.0: widening floating-point reduction instructions
   target/riscv: rvv-1.0: single-width scaling shift instructions
   target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
   target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
   target/riscv: rvv-1.0: remove integer extract instruction
   target/riscv: rvv-1.0: floating-point min/max instructions
   target/riscv: introduce floating-point rounding mode enum
   target/riscv: rvv-1.0: floating-point/integer type-convert
   target/riscv: rvv-1.0: widening floating-point/integer type-convert
   target/riscv: add "set round to odd" rounding mode helper function
   target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
   target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
   target/riscv: rvv-1.0: implement vstart CSR
   target/riscv: rvv-1.0: trigger illegal instruction exception if frm is
     not valid
   target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
   target/riscv: rvv-1.0: floating-point reciprocal square-root estimate
   target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
   target/riscv: set mstatus.SD bit when writing fp CSRs
   target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
   target/riscv: rvv-1.0: add vsetivli instruction
   target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
   target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
   target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm
     and vmorn.mm
   target/riscv: rvv-1.0: update opivv_vadc_check() comment

Greentime Hu (1):
   target/riscv: rvv-1.0: add vlenb register

Hsiangkai Wang (1):
   target/riscv: gdb: support vector registers for rv64 & rv32

LIU Zhiwei (3):
   target/riscv: rvv-1.0: add mstatus VS field
   target/riscv: rvv-1.0: add sstatus VS field
   target/riscv: rvv-1.0: add vcsr register

  target/riscv/cpu.c                      |   12 +-
  target/riscv/cpu.h                      |   85 +-
  target/riscv/cpu_bits.h                 |   10 +
  target/riscv/cpu_helper.c               |   15 +-
  target/riscv/csr.c                      |   92 +-
  target/riscv/fpu_helper.c               |   17 +-
  target/riscv/gdbstub.c                  |  184 ++
  target/riscv/helper.h                   |  435 ++-
  target/riscv/insn32.decode              |  294 +-
  target/riscv/insn_trans/trans_rvv.c.inc | 2423 +++++++++------
  target/riscv/internals.h                |   24 +-
  target/riscv/translate.c                |   74 +-
  target/riscv/vector_helper.c            | 3601 ++++++++++++-----------
  13 files changed, 4176 insertions(+), 3090 deletions(-)


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