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[PATCH 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::
From: |
Bin Meng |
Subject: |
[PATCH 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id |
Date: |
Mon, 18 Oct 2021 23:38:28 +0800 |
Using memory_region_init_ram(), which can't possibly handle vhost-user,
and can't work as expected with '-numa node,memdev' options.
Use MachineState::ram instead of manually initializing RAM memory
region, as well as by providing MachineClass::default_ram_id to
opt in to memdev scheme.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
hw/riscv/sifive_u.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index fc5790b8ce..0217006c27 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -528,7 +528,6 @@ static void sifive_u_machine_init(MachineState *machine)
const MemMapEntry *memmap = sifive_u_memmap;
SiFiveUState *s = RISCV_U_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
target_ulong firmware_end_addr, kernel_start_addr;
@@ -549,10 +548,8 @@ static void sifive_u_machine_init(MachineState *machine)
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* register RAM */
- memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
- machine->ram_size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
- main_mem);
+ machine->ram);
/* register QSPI0 Flash */
memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
@@ -748,6 +745,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc,
void *data)
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
mc->default_cpu_type = SIFIVE_U_CPU;
mc->default_cpus = mc->min_cpus;
+ mc->default_ram_id = "riscv.sifive.u.ram";
object_class_property_add_bool(oc, "start-in-flash",
sifive_u_machine_get_start_in_flash,
--
2.25.1
- [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id,
Bin Meng <=
- [PATCH 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Philippe Mathieu-Daudé, 2021/10/18
- Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Igor Mammedov, 2021/10/19