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[PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration
From: |
Richard Henderson |
Subject: |
[PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration |
Date: |
Mon, 18 Oct 2021 17:00:54 -0700 |
Move the MXL_RV* defines to enumerators.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_bits.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..e248c6bf6d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -364,9 +364,11 @@
#define MISA32_MXL 0xC0000000
#define MISA64_MXL 0xC000000000000000ULL
-#define MXL_RV32 1
-#define MXL_RV64 2
-#define MXL_RV128 3
+typedef enum {
+ MXL_RV32 = 1,
+ MXL_RV64 = 2,
+ MXL_RV128 = 3,
+} RISCVMXL;
/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
--
2.25.1
- [PATCH v4 00/16] target/riscv: Rationalize XLEN and operand length, Richard Henderson, 2021/10/18
- [PATCH v4 01/16] target/riscv: Move cpu_get_tb_cpu_state out of line, Richard Henderson, 2021/10/18
- [PATCH v4 02/16] target/riscv: Create RISCVMXL enumeration,
Richard Henderson <=
- [PATCH v4 06/16] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/18
- [PATCH v4 05/16] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/18
- [PATCH v4 03/16] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/18
- [PATCH v4 08/16] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/18
- [PATCH v4 04/16] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/18
- [PATCH v4 10/16] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/18
- [PATCH v4 07/16] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/18
- [PATCH v4 09/16] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/18