Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp

From:	Richard Henderson
Subject:	Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp
Date:	Wed, 20 Oct 2021 16:09:59 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/19/21 2:48 AM, Frédéric Pétrot wrote:

Support for a 128-bit satp. This is a bit more involved than necessary
because we took the opportunity to increase the page size to 16kB, and
change the page table geometry, which makes the page walk a bit more
parametrizable (variables instead of defines).
Note that is anyway a necessary step for the merging of the 32-bit and
64-bit riscv versions in a single executable.

Signed-off-by: Frédéric Pétrot<frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas<fabien.portas@grenoble-inp.org>
---
  target/riscv/cpu-param.h  |   9 +++-
  target/riscv/cpu_bits.h   |  10 ++++
  target/riscv/cpu_helper.c |  54 ++++++++++++++------
  target/riscv/csr.c        | 105 ++++++++++++++++++++++++++++++++------
  4 files changed, 144 insertions(+), 34 deletions(-)


Is there a spec for this?  I don't see anything in the 2021-10-06 draft...


r~

[Prev in Thread]

Current Thread

[Next in Thread]

Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, (continued)
- [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, Richard Henderson, 2021/10/20
- [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions, Richard Henderson, 2021/10/20
    - Re: [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/24
- [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns, Richard Henderson, 2021/10/20
- [PATCH v3 21/21] target/riscv: support for 128-bit satp, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp, Richard Henderson <=
    - Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp, Frédéric Pétrot, 2021/10/21
- [PATCH v3 15/21] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 15/21] target/riscv: support for 128-bit M extension, Richard Henderson, 2021/10/20
- [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support, Richard Henderson, 2021/10/20
- [PATCH v3 16/21] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 16/21] target/riscv: adding high part of some csrs, Richard Henderson, 2021/10/20
  - Re: [PATCH v3 16/21] target/riscv: adding high part of some csrs, Richard Henderson, 2021/10/20
- [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 19/21] target/riscv: actual functions to realize crs 128-bit insns, Richard Henderson, 2021/10/20

Prev by Date: Re: [PATCH v2 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id
Next by Date: Re: [PATCH v2 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id
Previous by thread: [PATCH v3 21/21] target/riscv: support for 128-bit satp
Next by thread: Re: [PATCH v3 21/21] target/riscv: support for 128-bit satp
Index(es):
- Date
- Thread