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[RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support

From: Ruinland Chuan-Tzu Tsai
Subject: [RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support
Date: Thu, 21 Oct 2021 23:09:18 +0800

Hi Alistair, Bin and all :

Sorry for bumping this stale topic.
As our last discussion, I have removed Kconfigs and meson options.
The custom CSR logic is in-built by default and whether a custom CSR
is presented on the accessing hart will be checked at runtime.

Changes from V4 :
Remove Kconfigs and meson options.
Make custom CSR handling logic self-contained.
Use g_hash_table_new instead of g_hash_table_new_full.

The performance slowdown could be easily tested with a simple program
running on linux-user mode :

/* test_csr.c */
#include <stdio.h>
#include <unistd.h>
#include <sys/time.h>

int main (int ac, char *av[]) {
   struct  timeval start;
   struct  timeval end;
   unsigned int loop_n = 999999 ;
   unsigned char i;
   unsigned char o;
   do {
       for(i=0; i<32; i++) { 
       #if defined(FCSR)
       __asm__("csrw fcsr, %0;"::"r"(i));
       __asm__("csrr %0, fcsr;":"=r"(o));
       #elif defined(UITB)
       __asm__("csrw 0x800, %0;"::"r"(i));
       __asm__("csrr %0, 0x800;":"=r"(o));
   } while (loop_n > 0);
   unsigned long diff = 1000000 * 
   printf("%f\n", (double)(diff)/1000000);
   return 0;

$ riscv64-linux-gnu-gcc -static -DUITB ./test_csr.c -o ./u
$ riscv64-linux-gnu-gcc -static -DFCSR ./test_csr.c -o ./f
$ qemu-riscv64 ./{u,f}

Cordially yours,
Ruinland Chuan-Tzu Tsai

Ruinland Chuan-Tzu Tsai (3):
  riscv: Adding Andes A25 and AX25 cpu models
  riscv: Introduce custom CSR hooks to riscv_csrrw()
  riscv: Enable custom CSR support for Andes AX25 and A25 CPUs

 target/riscv/andes_cpu_bits.h  | 129 +++++++++++++++++++++++
 target/riscv/cpu.c             |  39 +++++++
 target/riscv/cpu.h             |  15 ++-
 target/riscv/csr.c             |  38 +++++--
 target/riscv/csr_andes.c       | 183 +++++++++++++++++++++++++++++++++
 target/riscv/custom_csr_defs.h |   8 ++
 target/riscv/meson.build       |   1 +
 7 files changed, 404 insertions(+), 9 deletions(-)
 create mode 100644 target/riscv/andes_cpu_bits.h
 create mode 100644 target/riscv/csr_andes.c
 create mode 100644 target/riscv/custom_csr_defs.h


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