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Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length

From: LIU Zhiwei
Subject: Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
Date: Mon, 25 Oct 2021 17:24:11 +0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 2021/10/22 下午11:50, Richard Henderson wrote:
On 10/22/21 1:26 AM, LIU Zhiwei wrote:
As the specification said, "PC bits above XLEN are ignored, and when
the PC is written, it is sign-extended to fill the widest supported XLEN."
We still need special process of PC for exceptions or jump instructions.

I have two methods to implement  PC register access,
but not sure which is the right way.

First, normally process the PC register as the specification points.
That means expanding  the PC when setting the global TCGv variable
cpu_pc, and truncating the pc_first and  pc_next fields in
DisasContextBase before decoding instructions.    I am not sure
whether the sign-extended pc is compatible with QEMU common code.

I think extending on write is the correct thing.

Thanks. I will pick this way.

Jumps, exception entry and return, gdb write.

If we carefully process jumps and gdb write, I think we can omit exception entry and return. Is it right?

Note that the read from PC for translation is in cpu_get_tb_cpu_state, before translation.  You should not need to change anything wrt pc_first/pc_next/etc, because it will already have been done.

Good! Thanks.

Best Regards,

Second,  ignore ignore the PC special process for jump instructions.
Just expand or truncate the PC register when exception processing,
gdb read, or cpu dump registers. It is not a stright way,  but I think it is still right.

I think you could make it work that way, but I don't know that it's less difficult, or that you'd have fewer changes.


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