[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[PATCH v17 0/8] RISC-V Pointer Masking implementation

From: Alexey Baturo
Subject: [PATCH v17 0/8] RISC-V Pointer Masking implementation
Date: Mon, 25 Oct 2021 20:36:01 +0300

Rebased against the latest tree

Renamed pm into pointer_masking in machine state.

Addressed Richard's comments from previous series.

Rebased QEMU and addressed Richard's comment.

Updated function for adjusting address with pointer masking to allocate and use 
temp register.

Addressed a few style issues Alistair mentioned in the previous review.

Alexey Baturo (7):
  target/riscv: Add J-extension into RISC-V
  target/riscv: Add CSR defines for RISC-V PM extension
  target/riscv: Support CSRs required for RISC-V PM extension except for
    the h-mode
  target/riscv: Add J extension state description
  target/riscv: Print new PM CSRs in QEMU logs
  target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types
    of instructions
  target/riscv: Allow experimental J-ext to be turned on

Anatoly Parshintsev (1):
  target/riscv: Implement address masking functions required for RISC-V
    Pointer Masking extension

 target/riscv/cpu.c                      |  13 ++
 target/riscv/cpu.h                      |  15 ++
 target/riscv/cpu_bits.h                 |  96 ++++++++
 target/riscv/cpu_helper.c               |  18 ++
 target/riscv/csr.c                      | 285 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rva.c.inc |   3 +
 target/riscv/insn_trans/trans_rvd.c.inc |   2 +
 target/riscv/insn_trans/trans_rvf.c.inc |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc |   2 +
 target/riscv/machine.c                  |  27 +++
 target/riscv/translate.c                |  43 ++++
 11 files changed, 506 insertions(+)


reply via email to

[Prev in Thread] Current Thread [Next in Thread]