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[PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rm
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From: |
Anup Patel |
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Subject: |
[PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback |
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Date: |
Tue, 26 Oct 2021 12:12:13 +0530 |
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu.h | 19 +++++++++++++++++++
target/riscv/cpu_helper.c | 14 ++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7182fadd21..ef4298dc69 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -239,6 +239,18 @@ struct CPURISCVState {
uint64_t (*rdtime_fn)(uint32_t);
uint32_t rdtime_fn_arg;
+ /* machine specific AIA ireg read-modify-write callback */
+#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein) \
+ ((((__vgein) & 0x3f) << 24) | (((__virt) & 0x1) << 20) | \
+ (((__priv) & 0x3) << 16) | (__isel & 0xffff))
+#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
+#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
+#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 20) & 0x1)
+#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 24) & 0x3f)
+ int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
+ target_ulong *val, target_ulong new_val, target_ulong write_mask);
+ void *aia_ireg_rmw_fn_arg[4];
+
/* True if in debugger mode. */
bool debugger;
#endif
@@ -380,6 +392,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t
mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
uint32_t arg);
+void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
+ int (*rmw_fn)(void *arg,
+ target_ulong reg,
+ target_ulong *val,
+ target_ulong new_val,
+ target_ulong write_mask),
+ void *rmw_fn_arg);
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 04df3792a8..d70def1da8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -375,6 +375,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t
(*fn)(uint32_t),
env->rdtime_fn_arg = arg;
}
+void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
+ int (*rmw_fn)(void *arg,
+ target_ulong reg,
+ target_ulong *val,
+ target_ulong new_val,
+ target_ulong write_mask),
+ void *rmw_fn_arg)
+{
+ if (priv <= PRV_M) {
+ env->aia_ireg_rmw_fn[priv] = rmw_fn;
+ env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
+ }
+}
+
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {
--
2.25.1
- [PATCH v4 00/22] QEMU RISC-V AIA support, Anup Patel, 2021/10/26
- [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2021/10/26
- [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/10/26
- [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2021/10/26
- [PATCH v4 06/22] target/riscv: Add AIA cpu feature, Anup Patel, 2021/10/26
- [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/10/26
- [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts, Anup Patel, 2021/10/26
- [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/10/26
- [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback,
Anup Patel <=
- [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/10/26
- [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/10/26
- [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/10/26
- [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/10/26
- [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/10/26
- [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/10/26
- [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/10/26
- [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2021/10/26
- [PATCH v4 17/22] target/riscv: Allow users to force enable AIA CSRs in HART, Anup Patel, 2021/10/26
- [PATCH v4 18/22] hw/intc: Add RISC-V AIA APLIC device emulation, Anup Patel, 2021/10/26