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Re: [PATCH v4 04/22] target/riscv: Improve delivery of guest external in
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts |
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Date: |
Mon, 1 Nov 2021 09:35:21 +1000 |
On Tue, Oct 26, 2021 at 5:41 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> The guest external interrupts from an interrupt controller are
> delivered only when the Guest/VM is running (i.e. V=1). This means
> any guest external interrupt which is triggered while the Guest/VM
> is not running (i.e. V=0) will be missed on QEMU resulting in Guest
> with sluggish response to serial console input and other I/O events.
>
> To solve this, we check and inject interrupt after setting V=1.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index bb7ac9890b..04df3792a8 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -287,6 +287,19 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool
> enable)
> }
>
> env->virt = set_field(env->virt, VIRT_ONOFF, enable);
> +
> + if (enable) {
> + /*
> + * The guest external interrupts from an interrupt controller are
> + * delivered only when the Guest/VM is running (i.e. V=1). This means
> + * any guest external interrupt which is triggered while the Guest/VM
> + * is not running (i.e. V=0) will be missed on QEMU resulting in guest
> + * with sluggish response to serial console input and other I/O
> events.
> + *
> + * To solve this, we check and inject interrupt after setting V=1.
> + */
> + riscv_cpu_update_mip(env_archcpu(env), 0, 0);
> + }
> }
>
> bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env)
> --
> 2.25.1
>
>
- [PATCH v4 00/22] QEMU RISC-V AIA support, Anup Patel, 2021/10/26
- [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2021/10/26
- [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/10/26
- [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2021/10/26
- [PATCH v4 06/22] target/riscv: Add AIA cpu feature, Anup Patel, 2021/10/26
- [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/10/26
- [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts, Anup Patel, 2021/10/26
- Re: [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts,
Alistair Francis <=
- [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/10/26
- [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2021/10/26
- [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/10/26
- [PATCH v4 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/10/26
- [PATCH v4 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/10/26
- [PATCH v4 12/22] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/10/26
- [PATCH v4 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/10/26
- [PATCH v4 14/22] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/10/26
- [PATCH v4 15/22] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/10/26
- [PATCH v4 16/22] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2021/10/26