Re: [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs

[Anup Patel]

On Tue, Nov 2, 2021 at 4:22 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Nov 2, 2021 at 6:24 PM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Tue, Nov 2, 2021 at 12:22 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > On Tue, Oct 26, 2021 at 2:43 PM Anup Patel <anup.patel@wdc.com> wrote:
> > > >
> > > > A hypervsior can optionally take guest external interrupts using
> > >
> > > typo: hypervisor
> >
> > Okay, I will update.
> >
> > >
> > > > SGEIP bit of hip and hie CSRs.
> > > >
> > > > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > > > ---
> > > >  target/riscv/cpu.c      |  3 ++-
> > > >  target/riscv/cpu_bits.h |  3 +++
> > > >  target/riscv/csr.c      | 18 +++++++++++-------
> > > >  3 files changed, 16 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > index 788fa0b11c..0460a3972b 100644
> > > > --- a/target/riscv/cpu.c
> > > > +++ b/target/riscv/cpu.c
> > > > @@ -365,6 +365,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> > > >          env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, 
> > > > env->misa_mxl);
> > > >      }
> > > >      env->mcause = 0;
> > > > +    env->miclaim = MIP_SGEIP;
> > > >      env->pc = env->resetvec;
> > > >      env->two_stage_lookup = false;
> > > >  #endif
> > > > @@ -598,7 +599,7 @@ static void riscv_cpu_init(Object *obj)
> > > >      cpu_set_cpustate_pointers(cpu);
> > > >
> > > >  #ifndef CONFIG_USER_ONLY
> > > > -    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12);
> > > > +    qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX);
> > > >  #endif /* CONFIG_USER_ONLY */
> > > >  }
> > > >
> > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > > > index cffcd3a5df..8a5a4cde95 100644
> > > > --- a/target/riscv/cpu_bits.h
> > > > +++ b/target/riscv/cpu_bits.h
> > > > @@ -498,6 +498,8 @@ typedef enum RISCVException {
> > > >  #define IRQ_S_EXT                          9
> > > >  #define IRQ_VS_EXT                         10
> > > >  #define IRQ_M_EXT                          11
> > > > +#define IRQ_S_GEXT                         12
> > > > +#define IRQ_LOCAL_MAX                      13
> > >
> > > The IRQ_LOCAL_MAX should be XLEN long, not 13.
> >
> > The IRQ_LOCAL_MAX here represents local interrupts
> > standardized by the RISC-V privilege spec. This value
>
> The standardardized IRQ number is 16.

Max local IRQ as 13 is more conservative and better (IMO)
because we are not including any undefined local IRQ.

I also totally fine changing max local IRQ to 16 as well.

>
> > will change only when more local interrupts are
> > standardized by the RISC-V privilege spec.
>
> We should leave room for platform / custom IRQ as it is already
> defined by the priv spec.

custom local IRQs are not going to be accepted in the first 16 local
IRQs.

The AIA spec defines a sparse numbering scheme for both
standard/custom local IRQs beyond 16. The AIA spec will also
maintain a table of defined local IRQs.

IMO, we should deal with custom local IRQs as when they show
up and standard local IRQs should always get first class treatment.

Regards,
Anup

>
> Regards,
> Bin