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Re: [PATCH v2 4/7] target/riscv: cpu: Add a config option for native deb
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 4/7] target/riscv: cpu: Add a config option for native debug |
Date: |
Wed, 3 Nov 2021 15:59:18 +1000 |
On Sat, Oct 30, 2021 at 11:57 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Add a config option to enable support for native M-mode debug.
> This is disabled by default and can be enabled with 'debug=true'.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> Changes in v2:
> - change the config option to 'disabled' by default
>
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu.c | 5 +++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1fb13e8b94..b2301425c2 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -75,6 +75,7 @@ enum {
> RISCV_FEATURE_MMU,
> RISCV_FEATURE_PMP,
> RISCV_FEATURE_EPMP,
> + RISCV_FEATURE_DEBUG,
> RISCV_FEATURE_MISA
> };
>
> @@ -327,6 +328,7 @@ struct RISCVCPU {
> bool mmu;
> bool pmp;
> bool epmp;
> + bool debug;
> uint64_t resetvec;
> } cfg;
> };
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7061ae05fb..84116768ce 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -448,6 +448,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
> }
>
> + if (cpu->cfg.debug) {
> + set_feature(env, RISCV_FEATURE_DEBUG);
> + }
> +
> set_resetvec(env, cpu->cfg.resetvec);
>
> /* Validate that MISA_MXL is set properly. */
> @@ -631,6 +635,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
>
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>
> --
> 2.25.1
>
>
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