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[PATCH v2 09/14] target/riscv: Relax debug check for pm write
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v2 09/14] target/riscv: Relax debug check for pm write |
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Date: |
Wed, 10 Nov 2021 15:04:47 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..74c0b788fd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1445,6 +1445,9 @@ static bool check_pm_current_disabled(CPURISCVState *env,
int csrno)
int csr_priv = get_field(csrno, 0x300);
int pm_current;
+ if (env->debugger) {
+ return false;
+ }
/*
* If priv lvls differ that means we're accessing csr from higher priv lvl,
* so allow the access
--
2.25.1
- Re: [PATCH v2 04/14] target/riscv: Use gdb xml according to max mxlen, (continued)
[PATCH v2 06/14] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/10
[PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/10
[PATCH v2 08/14] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/10
[PATCH v2 09/14] target/riscv: Relax debug check for pm write,
LIU Zhiwei <=
[PATCH v2 10/14] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/10
[PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/10
[PATCH v2 12/14] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/10