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[PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN
From: |
LIU Zhiwei |
Subject: |
[PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN |
Date: |
Thu, 11 Nov 2021 13:57:56 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index f5aabd5263..41c7c88904 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -739,7 +739,8 @@ static bool amo_check(DisasContext *s, arg_rwdvm* a)
(!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
vext_check_reg(s, a->rd, false) &&
vext_check_reg(s, a->rs2, false) &&
- ((1 << s->sew) <= sizeof(target_ulong)) &&
+ /* TODO: RV128 could allow 128-bit atomics */
+ ((1 << s->sew) <= (get_xl(s) == MXL_RV32 ? 4 : 8)) &&
((1 << s->sew) >= 4));
}
--
2.25.1
- Re: [PATCH v3 11/20] target/riscv: Split pm_enabled into mask and base, (continued)
- [PATCH v3 12/20] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/11
- [PATCH v3 13/20] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v3 14/20] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v3 15/20] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/11
- [PATCH v3 16/20] target/riscv: Ajdust vector atomic check with XLEN,
LIU Zhiwei <=
- [PATCH v3 17/20] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/11
- [PATCH v3 18/20] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/11
- [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v3 20/20] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/11