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Re: [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN
From: |
Alistair Francis |
Subject: |
Re: [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN |
Date: |
Mon, 15 Nov 2021 14:27:43 +1000 |
On Fri, Nov 12, 2021 at 1:54 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> The read from PC for translation is in cpu_get_tb_cpu_state, before
> translation.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 9eeed38c7e..4c048cc266 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -70,8 +70,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
> *pc,
> target_ulong *cs_base, uint32_t *pflags)
> {
> uint32_t flags = 0;
> + RISCVMXL xl = cpu_get_xl(env);
>
> - *pc = env->pc;
> + *pc = xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
> *cs_base = 0;
>
> if (riscv_has_ext(env, RVV)) {
> @@ -127,7 +128,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env,
> target_ulong *pc,
> }
> #endif
>
> - flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
> + flags = FIELD_DP32(flags, TB_FLAGS, XL, xl);
>
> *pflags = flags;
> }
> --
> 2.25.1
>
>
- [PATCH v4 00/20] Support UXL filed in xstatus, LIU Zhiwei, 2021/11/11
- [PATCH v4 01/20] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/11
- [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2021/11/11
- Re: [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN,
Alistair Francis <=
- [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/11
- [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/11
- [PATCH v4 06/20] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/11
- [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 08/20] target/riscv: Create current pm fields in env, LIU Zhiwei, 2021/11/11