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Re: [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN |
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Date: |
Tue, 16 Nov 2021 13:14:02 +1000 |
On Fri, Nov 12, 2021 at 1:58 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Write mask is representing the bits we care about.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
> target/riscv/op_helper.c | 3 ++-
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index e51dbc41c5..40c81421f2 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -486,7 +486,7 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
> return do_csrw(ctx, a->csr, src);
> }
>
> - TCGv mask = tcg_constant_tl(-1);
> + TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX : -1);
> return do_csrrw(ctx, a->rd, a->csr, src, mask);
> }
>
> @@ -537,7 +537,7 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
> return do_csrw(ctx, a->csr, src);
> }
>
> - TCGv mask = tcg_constant_tl(-1);
> + TCGv mask = tcg_constant_tl(get_xl(ctx) == MXL_RV32 ? UINT32_MAX : -1);
> return do_csrrw(ctx, a->rd, a->csr, src, mask);
> }
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 095d39671b..561e156bec 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr)
>
> void helper_csrw(CPURISCVState *env, int csr, target_ulong src)
> {
> - RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1);
> + target_ulong mask = cpu_get_xl(env) == MXL_RV32 ? UINT32_MAX : -1;
> + RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask);
>
> if (ret != RISCV_EXCP_NONE) {
> riscv_raise_exception(env, ret, GETPC());
> --
> 2.25.1
>
>
- Re: [PATCH v4 02/20] target/riscv: Sign extend pc for different XLEN, (continued)
- [PATCH v4 03/20] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 04/20] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/11
- [PATCH v4 05/20] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/11
- [PATCH v4 06/20] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/11
- [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/11
- Re: [PATCH v4 07/20] target/riscv: Adjust csr write mask with XLEN,
Alistair Francis <=
- [PATCH v4 08/20] target/riscv: Create current pm fields in env, LIU Zhiwei, 2021/11/11
- [PATCH v4 09/20] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2021/11/11
- [PATCH v4 10/20] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/11
- [PATCH v4 11/20] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/11
- [PATCH v4 12/20] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/11