Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

[Frédéric Pétrot]

On 23/11/2021 07:09, Alistair Francis wrote:
> On Sat, Nov 13, 2021 at 1:07 AM Frédéric Pétrot
> <frederic.petrot@univ-grenoble-alpes.fr> wrote:
> > +static bool rv128_needed(void *opaque)
> > +{
> > +    RISCVCPU *cpu = opaque;
> > +    CPURISCVState *env = &cpu->env;
> > +
> > +    return env->misa_mxl_max == MXL_RV128;
> > +}
>
> I think it would just be better to use riscv_cpu_mxl() directly
> instead of adding a new function here.

  Ok, thanks.
  I was doing that because as Zhiwei is progressing on the dynamic handling
  of xlen, in the end the "current" mxl could be different from mxl_max, and
  some state to be saved might live in the registers upper 64-bit.
  But you are quite right that we are not there yet, so I'll do that.

  Frédéric
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