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[PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comme
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From: |
frank . chang |
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Subject: |
[PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment |
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Date: |
Mon, 29 Nov 2021 11:03:36 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions is
moved to Section 11.4 in RVV v1.0 spec. Update the comment, no
functional changes.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 33ef7926e64..47eb3119cbe 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1613,7 +1613,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
/*
* For vadc and vsbc, an illegal instruction exception is raised if the
- * destination vector register is v0 and LMUL > 1. (Section 12.4)
+ * destination vector register is v0 and LMUL > 1. (Section 11.4)
*/
static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
{
--
2.25.1
- [PATCH v10 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, (continued)
- [PATCH v10 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/11/28
- [PATCH v10 68/77] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/11/28
- [PATCH v10 06/77] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/11/28
- [PATCH v10 69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/11/28
- [PATCH v10 70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/11/28
- [PATCH v10 72/77] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/11/28
- [PATCH v10 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/11/28
- [PATCH v10 71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/11/28
- [PATCH v10 74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/11/28
- [PATCH v10 75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/11/28
- [PATCH v10 76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment,
frank . chang <=
- [PATCH v10 77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions, frank . chang, 2021/11/28
- [PATCH v10 13/77] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/11/28
- [PATCH v10 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/11/28
- [PATCH v10 48/77] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/11/28
- [PATCH v10 45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/11/28
- [PATCH v10 53/77] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2021/11/28
- [PATCH v10 56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/11/28
- [PATCH v10 52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/11/28