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Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target
From: |
Richard Henderson |
Subject: |
Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target |
Date: |
Mon, 29 Nov 2021 11:47:17 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 |
On 11/28/21 2:57 PM, Frédéric Pétrot wrote:
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.
Thanks again for the reviews and suggestions.
v6:
- support for '-cpu rv128' in qemu-system-riscv64 to handle 128-bit
executables (no more qemu-system-riscv128)
- remove useless (and buggy) big-endian support in lq/sq
It seems like you haven't tested this with linux-user?
There are build problems:
In file included from /home/rth/qemu/qemu/include/semihosting/console.h:12,
from ../qemu/linux-user/semihost.c:14:
../qemu/target/riscv/cpu.h:485:33: error: unknown type name ‘Int128’
485 | Int128 *ret_value,
| ^~~~~~
../qemu/target/riscv/cpu.h:486:33: error: unknown type name ‘Int128’
486 | Int128 new_value, Int128 write_mask);
| ^~~~~~
../qemu/target/riscv/cpu.h:486:51: error: unknown type name ‘Int128’
486 | Int128 new_value, Int128 write_mask);
| ^~~~~~
../qemu/target/riscv/cpu.h:489:48: error: unknown type name ‘Int128’
489 | Int128 *ret_value);
| ^~~~~~
../qemu/target/riscv/cpu.h:491:46: error: unknown type name ‘Int128’
491 | Int128 new_value);
| ^~~~~~
../qemu/target/riscv/cpu.h:499:5: error: unknown type name
‘riscv_csr_read128_fn’
499 | riscv_csr_read128_fn read128;
| ^~~~~~~~~~~~~~~~~~~~
../qemu/target/riscv/cpu.h:500:5: error: unknown type name
‘riscv_csr_write128_fn’
500 | riscv_csr_write128_fn write128;
| ^~~~~~~~~~~~~~~~~~~~~
ninja: build stopped: subcommand failed.
r~
- [PATCH v6 07/18] target/riscv: setup everything for rv64 to support rv128 execution, (continued)
- [PATCH v6 07/18] target/riscv: setup everything for rv64 to support rv128 execution, Frédéric Pétrot, 2021/11/28
- [PATCH v6 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/11/28
- [PATCH v6 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/11/28
- [PATCH v6 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/11/28
- [PATCH v6 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/11/28
- [PATCH v6 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/11/28
- [PATCH v6 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/11/28
- Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target,
Richard Henderson <=
- Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target, Richard Henderson, 2021/11/29