[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target

From: Frédéric Pétrot
Subject: Re: [PATCH v6 00/18] Adding partial support for 128-bit riscv target
Date: Mon, 6 Dec 2021 16:00:34 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.2

Hi Richard,

On 29/11/2021 13:13, Richard Henderson wrote:
On 11/28/21 2:57 PM, Frédéric Pétrot wrote:
This series of patches provides partial 128-bit support for the riscv
target architecture, namely RVI and RVM, with minimal csr support.

Thanks again for the reviews and suggestions.

- support for '-cpu rv128' in qemu-system-riscv64 to handle 128-bit
   executables (no more qemu-system-riscv128)
- remove useless (and buggy) big-endian support in lq/sq

This also fails make check.  With

  ../qemu/configure --enable-debug --target-list=riscv64-linux-user,riscv64-softmmu,riscv32-softmmu,riscv32-linux-user

watch qemu-iotest 040 fail.

  I'm afraid this test and a few others (5 in total) fail on current master,
  too, with this 'configure' command line.
  I just did a fresh install to make sure I did not kill something in the rv128

  Note that if I add x86_64-softmmu to target-list, it runs like a charm, as
  it takes it as default choice.
  I did try to go back in time to find a working 040 with qemu-system-riscv32
  (the default choice of check when qemu-system-x86_64 does not exist) or
  qemu-system-riscv64, but I could not find one I could compile with my current
  So I suspect this is the syndrome of something that is (1) not of my doing
  (although it could have, for sure), and (2) above my understanding.

  Sorry for not being more helpful,


| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA,   Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70      Ad augusta  per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |

reply via email to

[Prev in Thread] Current Thread [Next in Thread]