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Re: [PATCH 1/7] hw/intc: sifive_plic: Add a reset function
From: |
Alistair Francis |
Subject: |
Re: [PATCH 1/7] hw/intc: sifive_plic: Add a reset function |
Date: |
Fri, 10 Dec 2021 12:12:05 +1000 |
On Wed, Dec 8, 2021 at 10:00 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Hi Alistair,
>
> On 12/8/21 07:42, Alistair Francis wrote:
> > From: Alistair Francis <alistair.francis@wdc.com>
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/intc/sifive_plic.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> > index 877e76877c..35f097799a 100644
> > --- a/hw/intc/sifive_plic.c
> > +++ b/hw/intc/sifive_plic.c
> > @@ -355,6 +355,17 @@ static const MemoryRegionOps sifive_plic_ops = {
> > }
> > };
> >
> > +static void sifive_plic_reset(DeviceState *dev)
> > +{
> > + SiFivePLICState *s = SIFIVE_PLIC(dev);
> > +
> > + memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources);
> > + memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs);
> > + memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words);
> > + memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
> > + memset(s->enable, 0, sizeof(uint32_t) * s->num_enables);
>
> Looking at sifive_plic_realize():
>
> - Should we reset the external IRQs in a default state?
Good point, I'll add that.
> - Shouldn't riscv_cpu_claim_interrupts() be called at reset?
I don't think so. riscv_cpu_claim_interrupts is a once and done call.
Alistair
>
> Note: parse_hart_config() name is slightly confusing since
> beside parsing, it also allocates addr_config. Maybe consider
> renaming?
- [PATCH 0/7] A collection of RISC-V cleanups and improvements, Alistair Francis, 2021/12/08
- [PATCH 2/7] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2021/12/08
- [PATCH 1/7] hw/intc: sifive_plic: Add a reset function, Alistair Francis, 2021/12/08
- [PATCH 3/7] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2021/12/08
- [PATCH 4/7] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2021/12/08
- [PATCH 5/7] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2021/12/08
- [PATCH 6/7] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2021/12/08
- [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2021/12/08