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[PATCH v11 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.V
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From: |
frank . chang |
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Subject: |
[PATCH v11 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty |
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Date: |
Fri, 10 Dec 2021 15:55:50 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9b5bd5d7b4..bb500afdeb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -502,6 +502,7 @@ static RISCVException read_mhartid(CPURISCVState *env, int
csrno,
static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
{
if ((status & MSTATUS_FS) == MSTATUS_FS ||
+ (status & MSTATUS_VS) == MSTATUS_VS ||
(status & MSTATUS_XS) == MSTATUS_XS) {
switch (xl) {
case MXL_RV32:
--
2.31.1
- [PATCH v11 00/77] support vector extension v1.0, frank . chang, 2021/12/10
- [PATCH v11 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/12/10
- [PATCH v11 02/77] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/12/10
- [PATCH v11 03/77] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/12/10
- [PATCH v11 04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty,
frank . chang <=
- [PATCH v11 05/77] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/12/10
- [PATCH v11 06/77] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/12/10
- [PATCH v11 09/77] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/12/10
- [PATCH v11 08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/12/10
- [PATCH v11 10/77] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/12/10
- [PATCH v11 07/77] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/12/10
- [PATCH v11 11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/12/10
- [PATCH v11 12/77] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/12/10
- [PATCH v11 13/77] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/12/10
- [PATCH v11 15/77] target/riscv: rvv-1.0: update check functions, frank . chang, 2021/12/10