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[PATCH v7 10/18] target/riscv: support for 128-bit bitwise instructions
From: |
Frédéric Pétrot |
Subject: |
[PATCH v7 10/18] target/riscv: support for 128-bit bitwise instructions |
Date: |
Mon, 13 Dec 2021 17:38:26 +0100 |
The 128-bit bitwise instructions do not need any function prototype change
as the functions can be applied independently on the lower and upper part of
the registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b6127783b3..4790dc0cb4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -448,7 +448,15 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
func(dest, src1, a->imm);
- gen_set_gpr(ctx, a->rd, dest);
+ if (get_xl(ctx) == MXL_RV128) {
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv desth = dest_gprh(ctx, a->rd);
+
+ func(desth, src1h, -(a->imm < 0));
+ gen_set_gpr128(ctx, a->rd, dest, desth);
+ } else {
+ gen_set_gpr(ctx, a->rd, dest);
+ }
return true;
}
@@ -462,7 +470,16 @@ static bool gen_logic(DisasContext *ctx, arg_r *a,
func(dest, src1, src2);
- gen_set_gpr(ctx, a->rd, dest);
+ if (get_xl(ctx) == MXL_RV128) {
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv src2h = get_gprh(ctx, a->rs2);
+ TCGv desth = dest_gprh(ctx, a->rd);
+
+ func(desth, src1h, src2h);
+ gen_set_gpr128(ctx, a->rd, dest, desth);
+ } else {
+ gen_set_gpr(ctx, a->rd, dest);
+ }
return true;
}
--
2.34.1
- [PATCH v7 01/18] exec/memop: Adding signedness to quad definitions, (continued)
- [PATCH v7 01/18] exec/memop: Adding signedness to quad definitions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/12/13
- [PATCH v7 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/12/13
- [PATCH v7 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/12/13
- [PATCH v7 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/12/13
- [PATCH v7 08/18] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/12/13
- [PATCH v7 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/12/13
- [PATCH v7 10/18] target/riscv: support for 128-bit bitwise instructions,
Frédéric Pétrot <=
- [PATCH v7 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/12/13
- [PATCH v7 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 07/18] target/riscv: setup everything for rv64 to support rv128 execution, Frédéric Pétrot, 2021/12/13
- [PATCH v7 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/12/13