[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by defa
|
From: |
Bin Meng |
|
Subject: |
Re: [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default |
|
Date: |
Mon, 20 Dec 2021 10:53:09 +0800 |
On Thu, Dec 16, 2021 at 12:55 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Let's enable the Hypervisor extension by default. This doesn't affect
> named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
> Hypervisor extensions by default for the virt machine.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Re: [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function, (continued)
- [PATCH v2 2/9] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2021/12/15
- [PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2021/12/15
- [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2021/12/15
- [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2021/12/15
- [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2021/12/15
- [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2021/12/15
- [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores, Alistair Francis, 2021/12/15
- Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores, Bin Meng, 2021/12/20
- [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency, Alistair Francis, 2021/12/15