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Re: [PATCH v4 3/3] target/riscv: Implement the stval/mtval illegal instr

From: Richard Henderson
Subject: Re: [PATCH v4 3/3] target/riscv: Implement the stval/mtval illegal instruction
Date: Mon, 20 Dec 2021 11:39:15 -0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0

On 12/19/21 10:49 PM, Alistair Francis wrote:
From: Alistair Francis<alistair.francis@wdc.com>

The stval and mtval registers can optionally contain the faulting
instruction on an illegal instruction exception. This patch adds support
for setting the stval and mtval registers.

The RISC-V spec states that "The stval register can optionally also be
used to return the faulting instruction bits on an illegal instruction
exception...". In this case we are always writing the value on an
illegal instruction.

This doesn't match all CPUs (some CPUs won't write the data), but in
QEMU let's just populate the value on illegal instructions. This won't
break any guest software, but will provide more information to guests.

Signed-off-by: Alistair Francis<alistair.francis@wdc.com>
  target/riscv/cpu.h        | 2 ++
  target/riscv/cpu_helper.c | 3 +++
  target/riscv/translate.c  | 3 +++
  3 files changed, 8 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


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