Re: [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu

[Atish Patra]

On Thu, Nov 4, 2021 at 4:11 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Tue, Oct 26, 2021 at 4:02 AM Atish Patra <atish.patra@wdc.com> wrote:
> >
> > The PMU counters are supported via cpu config "Counters" which doesn't
> > indicate the correct purpose of those counters.
> >
> > Rename the config property to pmu to indicate that these counters
> > are performance monitoring counters. This aligns with cpu options for
> > ARM architecture as well.
> >
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> >  target/riscv/cpu.c | 2 +-
> >  target/riscv/cpu.h | 2 +-
> >  target/riscv/csr.c | 2 +-
> >  3 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 1d69d1887e63..3b55f5ed0036 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -598,7 +598,7 @@ static Property riscv_cpu_properties[] = {
> >      DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
> >      DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> >      DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
> > -    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> > +    DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
> >      DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> >      DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> >      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 9e55b2f5b170..ebc1a8754032 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -294,7 +294,7 @@ struct RISCVCPU {
> >          bool ext_zbb;
> >          bool ext_zbc;
> >          bool ext_zbs;
> > -        bool ext_counters;
> > +        bool ext_pmu;
> >          bool ext_ifencei;
> >          bool ext_icsr;
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index de484c74d3b4..c486eeaffeb8 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -64,7 +64,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
> >      RISCVCPU *cpu = RISCV_CPU(cs);
> >      int ctr_index;
> >
> > -    if (!cpu->cfg.ext_counters) {
> > +    if (!cpu->cfg.ext_pmu) {
> >          /* The Counters extensions is not enabled */
>
> %s/Counters extensions/PMU extension
>

Thanks. Fixed it.

> >          return RISCV_EXCP_ILLEGAL_INST;
> >      }
> > --
>
> Otherwise,
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>


-- 
Regards,
Atish