qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 0/3] Fix RVV calling incorrect RFV/RVD check functions bug


From: Alistair Francis
Subject: Re: [PATCH v2 0/3] Fix RVV calling incorrect RFV/RVD check functions bug
Date: Thu, 6 Jan 2022 08:30:47 +1000

On Wed, Jan 5, 2022 at 12:23 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> For vector widening and narrowing floating-point instructions, we should
> use require_scale_rvf() instead of require_rvf() to check whether the
> correspond RVF/RVD is enabled if either source or destination
> floating-point operand is double-width of SEW. Otherwise, illegal
> instruction exception should be raised.
>
> e.g. For SEW=16, if the source/destination floating-point operand is
> double-width of SEW, RVF needs to be enabled. Otherwise, an illegal
> instruction exception will be raised. Similarly, for SEW=32, RVD
> needs to be enabled.
>
> Changelog:
>
> v2:
>   * Fix patch title typos.
>   * Add missing Signed-off-by.
>
> Frank Chang (3):
>   target/riscv: rvv-1.0: Call the correct RVF/RVD check function for
>     widening fp insns
>   target/riscv: rvv-1.0: Call the correct RVF/RVD check function for
>     widening fp/int type-convert insns
>   target/riscv: rvv-1.0: Call the correct RVF/RVD check function for
>     narrowing fp/int type-convert insns

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/insn_trans/trans_rvv.c.inc | 78 ++++++++++++++++++-------
>  1 file changed, 57 insertions(+), 21 deletions(-)
>
> --
> 2.31.1
>
>



reply via email to

[Prev in Thread] Current Thread [Next in Thread]