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Re: [PATCH v4 04/11] target/riscv: pmu: Make number of counters configur
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable |
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Date: |
Fri, 7 Jan 2022 15:50:57 +0800 |
On Fri, Jan 7, 2022 at 10:18 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> The RISC-V privilege specification provides flexibility to implement
> any number of counters from 29 programmable counters. However, the QEMU
> implements all the counters.
>
> Make it configurable through pmu config parameter which now will indicate
> how many programmable counters should be implemented by the cpu.
>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 2 +-
> target/riscv/csr.c | 96 ++++++++++++++++++++++++++++++----------------
> 3 files changed, 65 insertions(+), 35 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Re: [PATCH v4 07/11] target/riscv: Support mcycle/minstret write operation, (continued)
[PATCH v4 01/11] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2022/01/06
[PATCH v4 08/11] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/01/06
[PATCH v4 02/11] target/riscv: Implement PMU CSR predicate function for S-mode, Atish Patra, 2022/01/06
[PATCH v4 04/11] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2022/01/06
[PATCH v4 09/11] target/riscv: Simplify counter predicate function, Atish Patra, 2022/01/06