[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be tu
From: |
Alistair Francis |
Subject: |
Re: [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on |
Date: |
Tue, 18 Jan 2022 08:53:42 +1000 |
On Wed, Dec 29, 2021 at 12:44 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 01239620ca..38cd11a8ae 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -636,6 +636,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
> DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
> + DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
>
> --
> 2.31.1
>
>
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- Re: [PATCH 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on,
Alistair Francis <=