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| From: | Weiwei Li |
| Subject: | Re: [PATCH v4 5/7] target/riscv: rvk: add CSR support for Zkr |
| Date: | Tue, 18 Jan 2022 16:14:36 +0800 |
| User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 |
在 2022/1/18 下午12:36, Alistair Francis 写道:
On Tue, Jan 11, 2022 at 1:53 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:- add SEED CSR - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/cpu_bits.h | 9 +++++ target/riscv/csr.c | 74 +++++++++++++++++++++++++++++++++++++++++ target/riscv/pmp.h | 8 +++-- 3 files changed, 88 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5a6d49aa64..65c708622b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -374,6 +374,9 @@ #define CSR_VSPMMASK 0x2c1 #define CSR_VSPMBASE 0x2c2 +/* Crypto Extension */ +#define CSR_SEED 0x015 + /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 @@ -628,4 +631,10 @@ typedef enum RISCVException { #define UMTE_U_PM_INSN U_PM_INSN #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) +/* seed CSR bits */ +#define SEED_OPST (0b11 << 30) +#define SEED_OPST_BIST (0b00 << 30) +#define SEED_OPST_WAIT (0b01 << 30) +#define SEED_OPST_ES16 (0b10 << 30) +#define SEED_OPST_DEAD (0b11 << 30) #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index adb3d4381d..9d93e72f68 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -22,6 +22,8 @@ #include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "qemu/guest-random.h" +#include "qapi/error.h" /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) @@ -222,6 +224,38 @@ static RISCVException epmp(CPURISCVState *env, int csrno) } #endif +/* Predicates */ +static RISCVException seed(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu = env_archcpu(env);New line between declarations and code please
OK.
+ if (!cpu->cfg.ext_zkr) { + return RISCV_EXCP_ILLEGAL_INST; + } +#if !defined(CONFIG_USER_ONLY) + if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) { + /* Hypervisor extension is supported */ + if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) { + if (env->mseccfg & MSECCFG_SSEED) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } else { + return RISCV_EXCP_ILLEGAL_INST; + } + } + } + if (env->priv == PRV_M) { + return RISCV_EXCP_NONE; + } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { + return RISCV_EXCP_NONE; + } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { + return RISCV_EXCP_NONE; + } else { + return RISCV_EXCP_ILLEGAL_INST; + } +#else + return RISCV_EXCP_NONE; +#endif +} + /* User Floating-Point CSRs */ static RISCVException read_fflags(CPURISCVState *env, int csrno, target_ulong *val) @@ -1785,6 +1819,39 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno, #endif +/* Crypto Extension */ +static int read_seed(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val = 0; + uint32_t return_status = SEED_OPST_ES16;Keep variable declarations first please
OK.
+ *val = (*val) | return_status; + if (return_status == SEED_OPST_ES16) { + uint16_t random_number; + Error *err = NULL; + if (qemu_guest_getrandom(&random_number, sizeof(random_number), + &err) < 0) {You can use qemu_guest_getrandom_nofail() instead and then not worry about this error handling.
OK. I'll update this.
+ qemu_log_mask(LOG_UNIMP, "Seed: Crypto failure: %s", + error_get_pretty(err)); + error_free(err); + return -1; + } + *val = (*val) | random_number; + } else if (return_status == SEED_OPST_BIST) { + /* Do nothing */ + } else if (return_status == SEED_OPST_WAIT) { + /* Do nothing */ + } else if (return_status == SEED_OPST_DEAD) { + /* Do nothing */ + } + return 0;RISCV_EXCP_NONE instead of 0
OK.
+} + +static RISCVException write_seed(CPURISCVState *env, int csrno, + target_ulong val) +{ + return RISCV_EXCP_NONE; +} + /* * riscv_csrrw - read and/or update control and status register * @@ -1823,6 +1890,10 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, return RISCV_EXCP_ILLEGAL_INST; } + if (!write_mask && (csrno == CSR_SEED)) { + return RISCV_EXCP_ILLEGAL_INST; + }I think it would be better to remove this and use a rmw_*() function instead. Then the read/write check can happen in the CSR access function Look at rmw_mip() for an example of implementing a rmw_*() function.
OK. I'll update this.
USEED and SEED fields are added for the check of seed csr. the other changes are to align with the new code for MSECCFG_SSEED and MSECCFG_SSEED.+ /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) { return RISCV_EXCP_ILLEGAL_INST; @@ -2011,6 +2082,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_TIME] = { "time", ctr, read_time }, [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, + /* Crypto Extension */ + [CSR_SEED] = { "seed", seed, read_seed, write_seed}, + #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ [CSR_MCYCLE] = { "mcycle", any, read_instret }, diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index a9a0b363a7..83135849bb 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -37,9 +37,11 @@ typedef enum { } pmp_am_t; typedef enum { - MSECCFG_MML = 1 << 0, - MSECCFG_MMWP = 1 << 1, - MSECCFG_RLB = 1 << 2 + MSECCFG_MML = 1 << 0, + MSECCFG_MMWP = 1 << 1, + MSECCFG_RLB = 1 << 2, + MSECCFG_USEED = 1 << 8, + MSECCFG_SSEED = 1 << 9Why are these all being changed? Alistair
Regards, Weiwei Li
} mseccfg_field_t; typedef struct { -- 2.17.1
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