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Re: [PATCH v6 22/22] target/riscv: Relax UXL field for debugging
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v6 22/22] target/riscv: Relax UXL field for debugging |
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Date: |
Wed, 19 Jan 2022 13:34:28 +1000 |
On Thu, Jan 13, 2022 at 10:23 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d944ee9caf..1037c6b15d 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -580,7 +580,7 @@ static RISCVException write_mstatus(CPURISCVState *env,
> int csrno,
> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> MSTATUS_TW | MSTATUS_VS;
>
> - if (xl != MXL_RV32) {
> + if (xl != MXL_RV32 || env->debugger) {
> /*
> * RV32: MPV and GVA are not in mstatus. The current plan is to
> * add them to mstatush. For now, we just don't support it.
> @@ -905,7 +905,7 @@ static RISCVException read_sstatus(CPURISCVState *env,
> int csrno,
> target_ulong *val)
> {
> target_ulong mask = (sstatus_v1_10_mask);
> - if (env->xl != MXL_RV32) {
> + if (env->xl != MXL_RV32 || env->debugger) {
> mask |= SSTATUS64_UXL;
> }
> /* TODO: Use SXL not MXL. */
> @@ -917,7 +917,8 @@ static RISCVException write_sstatus(CPURISCVState *env,
> int csrno,
> target_ulong val)
> {
> target_ulong mask = (sstatus_v1_10_mask);
> - if (env->xl != MXL_RV32) {
> +
> + if (env->xl != MXL_RV32 || env->debugger) {
> mask |= SSTATUS64_UXL;
> }
> target_ulong newval = (env->mstatus & ~mask) | (val & mask);
> --
> 2.25.1
>
>
- [PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base, (continued)
- [PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/13
- [PATCH v6 15/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/13
- [PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/13
- [PATCH v6 18/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/13
- [PATCH v6 19/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/13
- [PATCH v6 20/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/13
- [PATCH v6 22/22] target/riscv: Relax UXL field for debugging, LIU Zhiwei, 2022/01/13
- Re: [PATCH v6 22/22] target/riscv: Relax UXL field for debugging,
Alistair Francis <=